| Message ID | 20210608073603.2408-12-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: DDI buf trans cleaup and fixes | expand |
On Tue, 08 Jun 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Give RKL its own get_buf_trans() func. > > v2: Drop the FIXME since the spec was clarified to > indicate that TGL values are used for the HDMI/eDP cases. > > Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1 Holds for v2. > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > .../drm/i915/display/intel_ddi_buf_trans.c | 62 +++++++++++++++---- > 1 file changed, 51 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index ef9622ecf390..fcb67deb46dd 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -1497,10 +1497,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > if (crtc_state->port_clock > 270000) { > - if (IS_ROCKETLAKE(dev_priv)) { > - return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, > - n_entries); > - } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { > + if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { > return intel_get_buf_trans(&tgl_uy_combo_phy_ddi_translations_dp_hbr2, > n_entries); > } else { > @@ -1508,13 +1505,8 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > n_entries); > } > } else { > - if (IS_ROCKETLAKE(dev_priv)) { > - return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr, > - n_entries); > - } else { > - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, > - n_entries); > - } > + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, > + n_entries); > } > } > > @@ -1553,6 +1545,52 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, > return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > } > > +static const struct intel_ddi_buf_trans * > +rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + if (crtc_state->port_clock > 270000) > + return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); > + else > + return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr, n_entries); > +} > + > +static const struct intel_ddi_buf_trans * > +rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > + > + if (crtc_state->port_clock > 540000) { > + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3, > + n_entries); > + } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { > + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, > + n_entries); > + } else if (dev_priv->vbt.edp.low_vswing) { > + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, > + n_entries); > + } > + > + return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > +} > + > +static const struct intel_ddi_buf_trans * > +rkl_get_combo_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > + return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); > + else > + return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > +} > + > static const struct intel_ddi_buf_trans * > tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > @@ -1642,6 +1680,8 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) > encoder->get_buf_trans = tgl_get_combo_buf_trans; > else > encoder->get_buf_trans = adlp_get_dkl_buf_trans; > + } else if (IS_ROCKETLAKE(i915)) { > + encoder->get_buf_trans = rkl_get_combo_buf_trans; > } else if (DISPLAY_VER(i915) >= 12) { > if (intel_phy_is_combo(i915, phy)) > encoder->get_buf_trans = tgl_get_combo_buf_trans;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index ef9622ecf390..fcb67deb46dd 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1497,10 +1497,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (crtc_state->port_clock > 270000) { - if (IS_ROCKETLAKE(dev_priv)) { - return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, - n_entries); - } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { + if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { return intel_get_buf_trans(&tgl_uy_combo_phy_ddi_translations_dp_hbr2, n_entries); } else { @@ -1508,13 +1505,8 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, n_entries); } } else { - if (IS_ROCKETLAKE(dev_priv)) { - return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr, - n_entries); - } else { - return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, - n_entries); - } + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, + n_entries); } } @@ -1553,6 +1545,52 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } +static const struct intel_ddi_buf_trans * +rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (crtc_state->port_clock > 270000) + return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); + else + return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr, n_entries); +} + +static const struct intel_ddi_buf_trans * +rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + if (crtc_state->port_clock > 540000) { + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3, + n_entries); + } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { + return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, + n_entries); + } else if (dev_priv->vbt.edp.low_vswing) { + return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, + n_entries); + } + + return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + +static const struct intel_ddi_buf_trans * +rkl_get_combo_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) + return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); + else + return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + static const struct intel_ddi_buf_trans * tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -1642,6 +1680,8 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) encoder->get_buf_trans = tgl_get_combo_buf_trans; else encoder->get_buf_trans = adlp_get_dkl_buf_trans; + } else if (IS_ROCKETLAKE(i915)) { + encoder->get_buf_trans = rkl_get_combo_buf_trans; } else if (DISPLAY_VER(i915) >= 12) { if (intel_phy_is_combo(i915, phy)) encoder->get_buf_trans = tgl_get_combo_buf_trans;