| Message ID | 20210617103214.44217-1-jitao.shi@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid screen shift | expand |
Hi, Jitao: Jitao Shi <jitao.shi@mediatek.com> 於 2021年6月17日 週四 下午6:32寫道： > > The bridge chip "ANX7625" requires the packets on lanes to aligne at the end, > or ANX7625 will shift the screen. > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c > index ae403c67cbd9..4735e0092ffe 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -194,6 +194,8 @@ struct mtk_dsi { > struct clk *hs_clk; > > u32 data_rate; > + /* force dsi line end without dsi_null data */ > + bool force_dsi_end_without_null; > > unsigned long mode_flags; > enum mipi_dsi_pixel_format format; > @@ -499,6 +501,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) > DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); > } > > + if (dsi->force_dsi_end_without_null) { > + horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2; > + horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2; > + horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2; > + horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes; > + } > + > writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); > writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); > writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); > @@ -1095,6 +1104,10 @@ static int mtk_dsi_probe(struct platform_device *pdev) > dsi->bridge.of_node = dev->of_node; > dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; > > + if (dsi->next_bridge) > + dsi->force_dsi_end_without_null = of_property_read_bool(dsi->next_bridge->of_node, > + "force_dsi_end_without_null"); This patch looks good to me, but I could not find "force_dsi_end_without_null" in binding document. Regards, Chun-Kuang. > + > drm_bridge_add(&dsi->bridge); > > ret = component_add(&pdev->dev, &mtk_dsi_component_ops); > -- > 2.25.1
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index ae403c67cbd9..4735e0092ffe 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -194,6 +194,8 @@ struct mtk_dsi { struct clk *hs_clk; u32 data_rate; + /* force dsi line end without dsi_null data */ + bool force_dsi_end_without_null; unsigned long mode_flags; enum mipi_dsi_pixel_format format; @@ -499,6 +501,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); } + if (dsi->force_dsi_end_without_null) { + horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2; + horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2; + horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2; + horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes; + } + writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); @@ -1095,6 +1104,10 @@ static int mtk_dsi_probe(struct platform_device *pdev) dsi->bridge.of_node = dev->of_node; dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; + if (dsi->next_bridge) + dsi->force_dsi_end_without_null = of_property_read_bool(dsi->next_bridge->of_node, + "force_dsi_end_without_null"); + drm_bridge_add(&dsi->bridge); ret = component_add(&pdev->dev, &mtk_dsi_component_ops);
The bridge chip "ANX7625" requires the packets on lanes to aligne at the end, or ANX7625 will shift the screen. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_dsi.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)