| Message ID | 20210524103733.554878-1-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | clk: meson: rounding for fast clocks on 32-bit SoCs | expand |
Hi Jerome, Hi Stephen, On Mon, May 24, 2021 at 12:37 PM Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > > On the 32-bit Amlogic Meson8/8b/8m2 SoCs we run into a problem with the > fast HDMI PLL and it's OD (post-dividers). This clock tree can run at > up to approx. 3GHz. > This however causes a problem, because these rates require BIT(31) to > be usable. Unfortunately this is not the case with clk_ops.round_rate > on 32-bit systems. BIT(31) is reserved for the sign (+ or -). > > clk_ops.determine_rate does not suffer from this limitation. It uses > an int to signal any errors and can then take all availble 32 bits for > the clock rate. > > Changes since v1 from [0]: > - reworked the first patch so the the existing > divider_{ro_}round_rate_parent implementations are using the new > divider_{ro_}determine_rate implementations to avoid code duplication > (thanks Jerome for the suggestion) > - added a patch to switch the default clk_divider_{ro_}ops to use > .determine_rate instead of .round_rate as suggested by Jerome > (thanks) > - dropped a patch for the Meson PLL ops as these are independent from > the divider patches and Jerome has applied that one directly (thanks) > - added Jerome's Reviewed-by to the meson clk-regmap patch (thanks!) > - dropped the RFC prefix please let me know what you think about this v2 I am asking because clk-divider is widely used, so I'd appreciate if this gets some time in linux-next (so for example Kernel CI can test this and report issues if there are any). Best regards, Martin
On Fri 04 Jun 2021 at 19:18, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > Hi Jerome, Hi Stephen, > > On Mon, May 24, 2021 at 12:37 PM Martin Blumenstingl > <martin.blumenstingl@googlemail.com> wrote: >> >> On the 32-bit Amlogic Meson8/8b/8m2 SoCs we run into a problem with the >> fast HDMI PLL and it's OD (post-dividers). This clock tree can run at >> up to approx. 3GHz. >> This however causes a problem, because these rates require BIT(31) to >> be usable. Unfortunately this is not the case with clk_ops.round_rate >> on 32-bit systems. BIT(31) is reserved for the sign (+ or -). >> >> clk_ops.determine_rate does not suffer from this limitation. It uses >> an int to signal any errors and can then take all availble 32 bits for >> the clock rate. >> >> Changes since v1 from [0]: >> - reworked the first patch so the the existing >> divider_{ro_}round_rate_parent implementations are using the new >> divider_{ro_}determine_rate implementations to avoid code duplication >> (thanks Jerome for the suggestion) >> - added a patch to switch the default clk_divider_{ro_}ops to use >> .determine_rate instead of .round_rate as suggested by Jerome >> (thanks) >> - dropped a patch for the Meson PLL ops as these are independent from >> the divider patches and Jerome has applied that one directly (thanks) >> - added Jerome's Reviewed-by to the meson clk-regmap patch (thanks!) >> - dropped the RFC prefix > please let me know what you think about this v2 > I am asking because clk-divider is widely used, so I'd appreciate if > this gets some time in linux-next (so for example Kernel CI can test > this and report issues if there are any). > Looks good to me Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> > > Best regards, > Martin
Hi Stephen, On Mon, Jun 7, 2021 at 9:04 AM Jerome Brunet <jbrunet@baylibre.com> wrote: > > > On Fri 04 Jun 2021 at 19:18, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > > > Hi Jerome, Hi Stephen, > > > > On Mon, May 24, 2021 at 12:37 PM Martin Blumenstingl > > <martin.blumenstingl@googlemail.com> wrote: > >> > >> On the 32-bit Amlogic Meson8/8b/8m2 SoCs we run into a problem with the > >> fast HDMI PLL and it's OD (post-dividers). This clock tree can run at > >> up to approx. 3GHz. > >> This however causes a problem, because these rates require BIT(31) to > >> be usable. Unfortunately this is not the case with clk_ops.round_rate > >> on 32-bit systems. BIT(31) is reserved for the sign (+ or -). > >> > >> clk_ops.determine_rate does not suffer from this limitation. It uses > >> an int to signal any errors and can then take all availble 32 bits for > >> the clock rate. > >> > >> Changes since v1 from [0]: > >> - reworked the first patch so the the existing > >> divider_{ro_}round_rate_parent implementations are using the new > >> divider_{ro_}determine_rate implementations to avoid code duplication > >> (thanks Jerome for the suggestion) > >> - added a patch to switch the default clk_divider_{ro_}ops to use > >> .determine_rate instead of .round_rate as suggested by Jerome > >> (thanks) > >> - dropped a patch for the Meson PLL ops as these are independent from > >> the divider patches and Jerome has applied that one directly (thanks) > >> - added Jerome's Reviewed-by to the meson clk-regmap patch (thanks!) > >> - dropped the RFC prefix > > please let me know what you think about this v2 > > I am asking because clk-divider is widely used, so I'd appreciate if > > this gets some time in linux-next (so for example Kernel CI can test > > this and report issues if there are any). Do you have any comments on this series? I am fine with it skipping 5.14 as it's a change which affects multiple platforms. So I would like to use the time until the trees are opening for patches targeting 5.15 to iron out code-review comments. > Looks good to me > Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Thanks Jerome - I'll add it to v3 once I send it (assuming nothing major changes) Best regards, Martin
Quoting Martin Blumenstingl (2021-06-22 14:04:55) > Hi Stephen, > > On Mon, Jun 7, 2021 at 9:04 AM Jerome Brunet <jbrunet@baylibre.com> wrote: > > > > > > On Fri 04 Jun 2021 at 19:18, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > > > > > Hi Jerome, Hi Stephen, > > > > > > On Mon, May 24, 2021 at 12:37 PM Martin Blumenstingl > > > <martin.blumenstingl@googlemail.com> wrote: > > >> > > >> On the 32-bit Amlogic Meson8/8b/8m2 SoCs we run into a problem with the > > >> fast HDMI PLL and it's OD (post-dividers). This clock tree can run at > > >> up to approx. 3GHz. > > >> This however causes a problem, because these rates require BIT(31) to > > >> be usable. Unfortunately this is not the case with clk_ops.round_rate > > >> on 32-bit systems. BIT(31) is reserved for the sign (+ or -). > > >> > > >> clk_ops.determine_rate does not suffer from this limitation. It uses > > >> an int to signal any errors and can then take all availble 32 bits for > > >> the clock rate. > > >> > > >> Changes since v1 from [0]: > > >> - reworked the first patch so the the existing > > >> divider_{ro_}round_rate_parent implementations are using the new > > >> divider_{ro_}determine_rate implementations to avoid code duplication > > >> (thanks Jerome for the suggestion) > > >> - added a patch to switch the default clk_divider_{ro_}ops to use > > >> .determine_rate instead of .round_rate as suggested by Jerome > > >> (thanks) > > >> - dropped a patch for the Meson PLL ops as these are independent from > > >> the divider patches and Jerome has applied that one directly (thanks) > > >> - added Jerome's Reviewed-by to the meson clk-regmap patch (thanks!) > > >> - dropped the RFC prefix > > > please let me know what you think about this v2 > > > I am asking because clk-divider is widely used, so I'd appreciate if > > > this gets some time in linux-next (so for example Kernel CI can test > > > this and report issues if there are any). > Do you have any comments on this series? > I am fine with it skipping 5.14 as it's a change which affects > multiple platforms. > So I would like to use the time until the trees are opening for > patches targeting 5.15 to iron out code-review comments. > > > Looks good to me > > Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> > Thanks Jerome - I'll add it to v3 once I send it (assuming nothing > major changes) Looks ok to me. Will you resend?
On the 32-bit Amlogic Meson8/8b/8m2 SoCs we run into a problem with the fast HDMI PLL and it's OD (post-dividers). This clock tree can run at up to approx. 3GHz. This however causes a problem, because these rates require BIT(31) to be usable. Unfortunately this is not the case with clk_ops.round_rate on 32-bit systems. BIT(31) is reserved for the sign (+ or -). clk_ops.determine_rate does not suffer from this limitation. It uses an int to signal any errors and can then take all availble 32 bits for the clock rate. Changes since v1 from [0]: - reworked the first patch so the the existing divider_{ro_}round_rate_parent implementations are using the new divider_{ro_}determine_rate implementations to avoid code duplication (thanks Jerome for the suggestion) - added a patch to switch the default clk_divider_{ro_}ops to use .determine_rate instead of .round_rate as suggested by Jerome (thanks) - dropped a patch for the Meson PLL ops as these are independent from the divider patches and Jerome has applied that one directly (thanks) - added Jerome's Reviewed-by to the meson clk-regmap patch (thanks!) - dropped the RFC prefix [0] https://patchwork.kernel.org/project/linux-clk/cover/20210517203724.1006254-1-martin.blumenstingl@googlemail.com/ Martin Blumenstingl (3): clk: divider: Add re-usable determine_rate implementations clk: divider: Switch from .round_rate to .determine_rate by default clk: meson: regmap: switch to determine_rate for the dividers drivers/clk/clk-divider.c | 93 +++++++++++++++++++++++++--------- drivers/clk/meson/clk-regmap.c | 19 ++++--- include/linux/clk-provider.h | 6 +++ 3 files changed, 85 insertions(+), 33 deletions(-)