| Message ID | 20210622232711.3219697-2-kieran.bingham@ideasonboard.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | [1/2] clk: renesas: r8a779a0: Add the DU clock | expand |
Hi Kieran, On Wed, Jun 23, 2021 at 1:27 AM Kieran Bingham <kieran.bingham@ideasonboard.com> wrote: > The DU clock is added to the S3D1 clock parent. The Renesas BSP lists > S2D1 as the clock parent, however there is no S2 clock on this platform. > > S3D1 is chosen as a best effort guess and demonstrates functionality but > is not guaranteed to be correct. Makes sense. > Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.15. Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index acaf5a93f1d3..a1bd158defb5 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -167,6 +167,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0), DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0), DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0), + DEF_MOD("du", 411, R8A779A0_CLK_S3D1), DEF_MOD("fcpvd0", 508, R8A779A0_CLK_S3D1), DEF_MOD("fcpvd1", 509, R8A779A0_CLK_S3D1), DEF_MOD("hscif0", 514, R8A779A0_CLK_S1D2),
The DU clock is added to the S3D1 clock parent. The Renesas BSP lists S2D1 as the clock parent, however there is no S2 clock on this platform. S3D1 is chosen as a best effort guess and demonstrates functionality but is not guaranteed to be correct. Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com> --- drivers/clk/renesas/r8a779a0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+)