| Message ID | 20210625095000.3358973-3-mnhagan88@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | ARM: dts: NSP: add Meraki MX64/MX65 series | expand |
On Fri, Jun 25, 2021 at 11:52 AM Matthew Hagan <mnhagan88@gmail.com> wrote: > > MX64 & MX64W Hardware info: > - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz > - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) > - Storage: 1 GB (Micron MT29F8G08ABACA) > - Networking: BCM58625 internal switch (5x 1GbE ports) > - USB: 1x USB2.0 > - Serial: Internal header > - WLAN(MX64W only): 2x Broadcom BCM43520KMLG on the PCI bus > > This patch adds the Meraki MX64 series-specific bindings. Since some > devices make use of the older A0 SoC, changes need to be made to > accommodate this case, including removal of coherency options and > modification to the secondary-boot-reg. > > Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Removing the dma-coherent flags in the dts file seemed really odd until I read the text above. It would seem more logical to me to have a .dtsi file that has all the a0 revision specific changes, and include that from the dts file. On the other hand, the /chosen, /aliases and /memory nodes that you have in the .dtsi file should probably get moved into the .dts files, as these tend to be board specific settings, even if the examples you have are all the same. Arnd
On 25/06/2021 10:59, Arnd Bergmann wrote: > On Fri, Jun 25, 2021 at 11:52 AM Matthew Hagan <mnhagan88@gmail.com> wrote: >> MX64 & MX64W Hardware info: >> - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz >> - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) >> - Storage: 1 GB (Micron MT29F8G08ABACA) >> - Networking: BCM58625 internal switch (5x 1GbE ports) >> - USB: 1x USB2.0 >> - Serial: Internal header >> - WLAN(MX64W only): 2x Broadcom BCM43520KMLG on the PCI bus >> >> This patch adds the Meraki MX64 series-specific bindings. Since some >> devices make use of the older A0 SoC, changes need to be made to >> accommodate this case, including removal of coherency options and >> modification to the secondary-boot-reg. >> >> Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> > Removing the dma-coherent flags in the dts file seemed really odd until > I read the text above. It would seem more logical to me to have a .dtsi file > that has all the a0 revision specific changes, and include that from the > dts file. How about having separate bcm-nsp-ax and bcm-nsp-bx dtsi files with the appropriate secondary-boot-reg and dma-coherent (or lack of) properties, which then include bcm-nsp.dtsi. Thus we can also avoid use of /delete-property/. Would this be preferable? > > On the other hand, the /chosen, /aliases and /memory nodes that you have > in the .dtsi file should probably get moved into the .dts files, as these tend > to be board specific settings, even if the examples you have are all > the same. I did not come across any convention regarding this, though there are plenty of cases where the /chosen, /aliases and /memory nodes are defined in a .dtsi file and used by multiple similar boards. Also note in this case /aliases is defined in bcm-nsp.dtsi, not by me. Would we not prefer to avoid having 6x duplication? > Arnd > Matthew
On 6/25/21 10:26 AM, Matthew Hagan wrote: > On 25/06/2021 10:59, Arnd Bergmann wrote: > >> On Fri, Jun 25, 2021 at 11:52 AM Matthew Hagan <mnhagan88@gmail.com> wrote: >>> MX64 & MX64W Hardware info: >>> - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz >>> - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) >>> - Storage: 1 GB (Micron MT29F8G08ABACA) >>> - Networking: BCM58625 internal switch (5x 1GbE ports) >>> - USB: 1x USB2.0 >>> - Serial: Internal header >>> - WLAN(MX64W only): 2x Broadcom BCM43520KMLG on the PCI bus >>> >>> This patch adds the Meraki MX64 series-specific bindings. Since some >>> devices make use of the older A0 SoC, changes need to be made to >>> accommodate this case, including removal of coherency options and >>> modification to the secondary-boot-reg. >>> >>> Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> >> Removing the dma-coherent flags in the dts file seemed really odd until >> I read the text above. It would seem more logical to me to have a .dtsi file >> that has all the a0 revision specific changes, and include that from the >> dts file. > > How about having separate bcm-nsp-ax and bcm-nsp-bx dtsi files with the > appropriate secondary-boot-reg and dma-coherent (or lack of) > properties, which then include bcm-nsp.dtsi. Thus we can also avoid use > of /delete-property/. Would this be preferable? Is there any way that the Ax platforms could use a small shim between the boot loader and the kernel which could all of the necessary DT adaptation so the kernel only contains a single Device Tree source? Using something like this: https://github.com/zonque/pxa-impedance-matcher/ could be useful. > >> >> On the other hand, the /chosen, /aliases and /memory nodes that you have >> in the .dtsi file should probably get moved into the .dts files, as these tend >> to be board specific settings, even if the examples you have are all >> the same. > > I did not come across any convention regarding this, though there are > plenty of cases where the /chosen, /aliases and /memory nodes are > defined in a .dtsi file and used by multiple similar boards. Also note > in this case /aliases is defined in bcm-nsp.dtsi, not by me. Would we > not prefer to avoid having 6x duplication? > >> Arnd >> > Matthew >
On Fri, Jun 25, 2021 at 7:30 PM Florian Fainelli <f.fainelli@gmail.com> wrote: > On 6/25/21 10:26 AM, Matthew Hagan wrote: > > On 25/06/2021 10:59, Arnd Bergmann wrote: > > > > How about having separate bcm-nsp-ax and bcm-nsp-bx dtsi files with the > > appropriate secondary-boot-reg and dma-coherent (or lack of) > > properties, which then include bcm-nsp.dtsi. Thus we can also avoid use > > of /delete-property/. Would this be preferable? That sounds good to me. > Is there any way that the Ax platforms could use a small shim between > the boot loader and the kernel which could all of the necessary DT > adaptation so the kernel only contains a single Device Tree source? > > Using something like this: > > https://github.com/zonque/pxa-impedance-matcher/ > > could be useful. I don't think that's necessary here, but I wouldn't object if someone finds it useful and does the work. ;-) > >> On the other hand, the /chosen, /aliases and /memory nodes that you have > >> in the .dtsi file should probably get moved into the .dts files, as these tend > >> to be board specific settings, even if the examples you have are all > >> the same. > > > > I did not come across any convention regarding this, though there are > > plenty of cases where the /chosen, /aliases and /memory nodes are > > defined in a .dtsi file and used by multiple similar boards. Also note > > in this case /aliases is defined in bcm-nsp.dtsi, not by me. Would we > > not prefer to avoid having 6x duplication? We are not too consistent about this, and there are cases in which a .dtsi file is used for a family of boards using different SoCs rather than a particular SoC or SoC family. In the bcm-nsp.dtsi example you mention, I would move the aliases into the board files, mainly because there is no guarantee that each board exposes both uarts and all three on-chip ethernet ports. Note that the aliases are supposed to match whatever label you have on the board, not what the numbers are in the chip. Arnd
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f8f09c5066e7..83560b05f797 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -154,6 +154,10 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \ bcm958525xmc.dtb \ bcm958622hr.dtb \ bcm958623hr.dtb \ + bcm958625-meraki-mx64.dtb \ + bcm958625-meraki-mx64-a0.dtb \ + bcm958625-meraki-mx64w.dtb \ + bcm958625-meraki-mx64w-a0.dtb \ bcm958625hr.dtb \ bcm988312hr.dtb \ bcm958625k.dtb diff --git a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi new file mode 100644 index 000000000000..7c487c74fd10 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin). + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +#include "bcm958625-meraki-mx6x-common.dtsi" + +/ { + + keys { + compatible = "gpio-keys-polled"; + autorepeat; + poll-interval = <20>; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpioa 6 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + /* green:lan1-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <0>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 19 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* green:lan1-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <1>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 18 GPIO_ACTIVE_LOW>; + }; + + led-2 { + /* green:lan2-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <2>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; + }; + + led-3 { + /* green:lan2-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <3>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 20 GPIO_ACTIVE_LOW>; + }; + + led-4 { + /* green:lan3-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <4>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; + }; + + led-5 { + /* green:lan3-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <5>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; + }; + + led-6 { + /* green:lan4-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <6>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 28 GPIO_ACTIVE_LOW>; + }; + + led-7 { + /* green:lan4-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <7>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; + }; + + led-8 { + /* green:wan-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <8>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 30 GPIO_ACTIVE_LOW>; + }; + + led-9 { + /* green:wan-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <9>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 29 GPIO_ACTIVE_LOW>; + }; + + led-a { + /* amber:power */ + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_AMBER>; + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-b { + /* white:status */ + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + port@0 { + label = "lan1"; + reg = <0>; + }; + + port@1 { + label = "lan2"; + reg = <1>; + }; + + port@2 { + label = "lan3"; + reg = <2>; + }; + + port@3 { + label = "lan4"; + reg = <3>; + }; + + port@4 { + label = "wan"; + reg = <4>; + }; + + port@8 { + ethernet = <&amac2>; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts new file mode 100644 index 000000000000..f9c8180293ed --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64(A0)"; + compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp"; +}; + +&amac2 { + /delete-property/ dma-coherent; +}; + +&cpu1 { + secondary-boot-reg = <0xffff042c>; +}; + +&ehci0 { + /delete-property/ dma-coherent; +}; + +&i2c0 { + /delete-property/ dma-coherent; +}; + +&L2 { + /delete-property/ arm,io-coherent; + /delete-property/ prefetch-data; + /delete-property/ prefetch-instr; +}; + +&mailbox { + /delete-property/ dma-coherent; +}; + +&ohci0 { + /delete-property/ dma-coherent; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts new file mode 100644 index 000000000000..58addd69688a --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64"; + compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp"; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts new file mode 100644 index 000000000000..807720d21660 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64W with A0 SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64W(A0)"; + compatible = "meraki,mx64w-a0", "brcm,bcm58625", "brcm,nsp"; +}; + +&amac2 { + /delete-property/ dma-coherent; +}; + +&cpu1 { + secondary-boot-reg = <0xffff042c>; +}; + +&ehci0 { + /delete-property/ dma-coherent; +}; + +&i2c0 { + /delete-property/ dma-coherent; +}; + +&L2 { + /delete-property/ arm,io-coherent; + /delete-property/ prefetch-data; + /delete-property/ prefetch-instr; +}; + +&mailbox { + /delete-property/ dma-coherent; +}; + +&ohci0 { + /delete-property/ dma-coherent; +}; + +&pcie0 { + /delete-property/ dma-coherent; + status = "okay"; +}; + +&pcie1 { + /delete-property/ dma-coherent; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts new file mode 100644 index 000000000000..8d37cd56c093 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64W"; + compatible = "meraki,mx64w", "brcm,bcm58625", "brcm,nsp"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +};
MX64 & MX64W Hardware info: - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) - Storage: 1 GB (Micron MT29F8G08ABACA) - Networking: BCM58625 internal switch (5x 1GbE ports) - USB: 1x USB2.0 - Serial: Internal header - WLAN(MX64W only): 2x Broadcom BCM43520KMLG on the PCI bus This patch adds the Meraki MX64 series-specific bindings. Since some devices make use of the older A0 SoC, changes need to be made to accommodate this case, including removal of coherency options and modification to the secondary-boot-reg. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> --- arch/arm/boot/dts/Makefile | 4 + .../boot/dts/bcm958625-meraki-kingpin.dtsi | 163 ++++++++++++++++++ .../arm/boot/dts/bcm958625-meraki-mx64-a0.dts | 45 +++++ arch/arm/boot/dts/bcm958625-meraki-mx64.dts | 15 ++ .../boot/dts/bcm958625-meraki-mx64w-a0.dts | 55 ++++++ arch/arm/boot/dts/bcm958625-meraki-mx64w.dts | 23 +++ 6 files changed, 305 insertions(+) create mode 100644 arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w.dts