| Message ID | 20210615133950.693489-4-tabba@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: arm64: Fixed features for protected VMs | expand |
On Tue, Jun 15, 2021 at 02:39:40PM +0100, Fuad Tabba wrote: > Change the names of hcr_el2 register fields to match the Arm > Architecture Reference Manual. Easier for cross-referencing and > for grepping. > > Also, change the name of CPTR_EL2_RES1 to CPTR_NVHE_EL2_RES1, > because res1 bits are different for VHE. > > No functional change intended. > > Signed-off-by: Fuad Tabba <tabba@google.com> > --- > arch/arm64/include/asm/kvm_arm.h | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h > index 25d8a61888e4..bee1ba6773fb 100644 > --- a/arch/arm64/include/asm/kvm_arm.h > +++ b/arch/arm64/include/asm/kvm_arm.h > @@ -31,9 +31,9 @@ > #define HCR_TVM (UL(1) << 26) > #define HCR_TTLB (UL(1) << 25) > #define HCR_TPU (UL(1) << 24) > -#define HCR_TPC (UL(1) << 23) > +#define HCR_TPCP (UL(1) << 23) This one is a bit weird: the field is called TPCP if the CPU supports FEAT_DPB but is called TPC otherwise! So I don't think renaming it like this really makes anything better. Perhaps add a comment: #define HCR_TPC (UL(1) << 23) /* TPCP if FEAT_DPB */ ? Rest of the patch looks good: Acked-by: Will Deacon <will@kernel.org> Will
Hi Will, On Thu, Jul 1, 2021 at 2:01 PM Will Deacon <will@kernel.org> wrote: > > On Tue, Jun 15, 2021 at 02:39:40PM +0100, Fuad Tabba wrote: > > Change the names of hcr_el2 register fields to match the Arm > > Architecture Reference Manual. Easier for cross-referencing and > > for grepping. > > > > Also, change the name of CPTR_EL2_RES1 to CPTR_NVHE_EL2_RES1, > > because res1 bits are different for VHE. > > > > No functional change intended. > > > > Signed-off-by: Fuad Tabba <tabba@google.com> > > --- > > arch/arm64/include/asm/kvm_arm.h | 12 ++++++------ > > 1 file changed, 6 insertions(+), 6 deletions(-) > > > > diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h > > index 25d8a61888e4..bee1ba6773fb 100644 > > --- a/arch/arm64/include/asm/kvm_arm.h > > +++ b/arch/arm64/include/asm/kvm_arm.h > > @@ -31,9 +31,9 @@ > > #define HCR_TVM (UL(1) << 26) > > #define HCR_TTLB (UL(1) << 25) > > #define HCR_TPU (UL(1) << 24) > > -#define HCR_TPC (UL(1) << 23) > > +#define HCR_TPCP (UL(1) << 23) > > This one is a bit weird: the field is called TPCP if the CPU supports > FEAT_DPB but is called TPC otherwise! So I don't think renaming it like > this really makes anything better. Perhaps add a comment: > > #define HCR_TPC (UL(1) << 23) /* TPCP if FEAT_DPB */ I missed that. That's why it's referred to as Bit[23] in the diagram. I'll add the comment and revert its name. Thanks, /fuad > ? > > Rest of the patch looks good: > > Acked-by: Will Deacon <will@kernel.org> > > Will
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 25d8a61888e4..bee1ba6773fb 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -31,9 +31,9 @@ #define HCR_TVM (UL(1) << 26) #define HCR_TTLB (UL(1) << 25) #define HCR_TPU (UL(1) << 24) -#define HCR_TPC (UL(1) << 23) +#define HCR_TPCP (UL(1) << 23) #define HCR_TSW (UL(1) << 22) -#define HCR_TAC (UL(1) << 21) +#define HCR_TACR (UL(1) << 21) #define HCR_TIDCP (UL(1) << 20) #define HCR_TSC (UL(1) << 19) #define HCR_TID3 (UL(1) << 18) @@ -60,7 +60,7 @@ * The bits we set in HCR: * TLOR: Trap LORegion register accesses * RW: 64bit by default, can be overridden for 32bit VMs - * TAC: Trap ACTLR + * TACR: Trap ACTLR * TSC: Trap SMC * TSW: Trap cache operations by set/way * TWE: Trap WFE @@ -75,7 +75,7 @@ * PTW: Take a stage2 fault if a stage1 walk steps in device memory */ #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ - HCR_BSU_IS | HCR_FB | HCR_TAC | \ + HCR_BSU_IS | HCR_FB | HCR_TACR | \ HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ HCR_FMO | HCR_IMO | HCR_PTW ) #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF) @@ -274,8 +274,8 @@ #define CPTR_EL2_TTA (1 << 20) #define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT) #define CPTR_EL2_TZ (1 << 8) -#define CPTR_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 */ -#define CPTR_EL2_DEFAULT CPTR_EL2_RES1 +#define CPTR_NVHE_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */ +#define CPTR_EL2_DEFAULT CPTR_NVHE_EL2_RES1 /* Hyp Debug Configuration Register bits */ #define MDCR_EL2_E2TB_MASK (UL(0x3))
Change the names of hcr_el2 register fields to match the Arm Architecture Reference Manual. Easier for cross-referencing and for grepping. Also, change the name of CPTR_EL2_RES1 to CPTR_NVHE_EL2_RES1, because res1 bits are different for VHE. No functional change intended. Signed-off-by: Fuad Tabba <tabba@google.com> --- arch/arm64/include/asm/kvm_arm.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)