| Message ID | 20210707041249.29816-10-jason-jh.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add MediaTek SoC DRM (vdosys0) support for mt8195 | expand |
Hi, Jason: On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote: > Add datapath_con settings to support multi-layer output. What is multi-layer output? Why we need this? > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 15 ++++++++++++--- > 1 file changed, 12 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index 7504e86b167a..95fd5e00eb91 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -18,14 +18,17 @@ > #include "mtk_drm_ddp_comp.h" > > #define DISP_REG_OVL_INTEN 0x0004 > -#define OVL_FME_CPL_INT BIT(1) > +#define OVL_FME_CPL_INT BIT(1) > #define DISP_REG_OVL_INTSTA 0x0008 > #define DISP_REG_OVL_EN 0x000c > #define DISP_REG_OVL_RST 0x0014 > #define DISP_REG_OVL_ROI_SIZE 0x0020 > #define DISP_REG_OVL_DATAPATH_CON 0x0024 > -#define OVL_LAYER_SMI_ID_EN BIT(0) > -#define OVL_BGCLR_SEL_IN BIT(2) > +#define OVL_LAYER_SMI_ID_EN BIT(0) > +#define OVL_BGCLR_SEL_IN BIT(2) > +#define OVL_GCLAST_EN BIT(24) > +#define OVL_HDR_GCLAST_EN BIT(25) > +#define OVL_OUTPUT_CLAMP BIT(26) > #define DISP_REG_OVL_ROI_BGCLR 0x0028 > #define DISP_REG_OVL_SRC_CON 0x002c > #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n)) > @@ -222,6 +225,7 @@ void mtk_ovl_layer_on(struct device *dev, unsigned int idx, > unsigned int gmc_thrshd_l; > unsigned int gmc_thrshd_h; > unsigned int gmc_value; > + unsigned int datapatch_con; > struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); > > mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, > @@ -237,6 +241,11 @@ void mtk_ovl_layer_on(struct device *dev, unsigned int idx, > gmc_thrshd_h << 16 | gmc_thrshd_h << 24; > mtk_ddp_write(cmdq_pkt, gmc_value, > &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx)); > + > + datapatch_con = OVL_GCLAST_EN | OVL_HDR_GCLAST_EN | OVL_OUTPUT_CLAMP; > + mtk_ddp_write_mask(cmdq_pkt, datapatch_con, &ovl->cmdq_reg, ovl->regs, > + DISP_REG_OVL_DATAPATH_CON, datapatch_con); For mt8173 or other SoC, this does not turn on. Now you turn on this, would this influence other SoC? Regards, CK > + > mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs, > DISP_REG_OVL_SRC_CON, BIT(idx)); > }
On Wed, 2021-07-07 at 13:43 +0800, CK Hu wrote: > Hi, Jason: > > On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote: > > Add datapath_con settings to support multi-layer output. > > > What is multi-layer output? Why we need this? > Hi CK, This patch is not the multi-layer output fix up patch. The fix up patch is this one: https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/commit/drivers/gpu/drm/mediatek/mtk_disp_ovl.c?h=mediatek-drm-next&id=d41ff4dcf093885dcc253e3861834eea294827cb So this patch is not necessary for mt8195 DRM series patches. I'll remove this patch at the next version. By the way, this patches is for: 1. If GCLAST is not enabled, SMI will not know if the group is over. SMI will wait until the last signal is received before it starts to act. It may cause OVL can not receive any data from SMI. To support OVL multi-layer output, add datapath_con settings below: GCLAST_EN = BIT(24), enable last SMI signal of ovl group HDR_GCLAST_EN = BIT(25), enable last SMI signal of ovl AFBC group 2. After OUTPUT_CLAMP is enabled, the data will be rounded from 12-bit to 10-bit. Because the modules after OVL need 10-bit input currently. It may cause underflow problem, if there is no rounding to 10-bit. To support 10bit data rounding, add datapath_con settings below: OUTPUT_CLAMP = BIT(26), rounding data from 12-bit to 10-bit Regard, Jason-JH.Lin > > > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 15 ++++++++++++--- > > 1 file changed, 12 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > index 7504e86b167a..95fd5e00eb91 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > @@ -18,14 +18,17 @@ > > #include "mtk_drm_ddp_comp.h" > > > > #define DISP_REG_OVL_INTEN 0x0004 > > -#define OVL_FME_CPL_INT BIT(1) > > +#define OVL_FME_CPL_INT BIT(1) > > #define DISP_REG_OVL_INTSTA 0x0008 > > #define DISP_REG_OVL_EN 0x000c > > #define DISP_REG_OVL_RST 0x0014 > > #define DISP_REG_OVL_ROI_SIZE 0x0020 > > #define DISP_REG_OVL_DATAPATH_CON 0x0024 > > -#define OVL_LAYER_SMI_ID_EN BIT(0) > > -#define OVL_BGCLR_SEL_IN BIT(2) > > +#define OVL_LAYER_SMI_ID_EN BIT(0) > > +#define OVL_BGCLR_SEL_IN BIT(2) > > +#define OVL_GCLAST_EN BIT(24) > > +#define OVL_HDR_GCLAST_EN BIT(25) > > +#define OVL_OUTPUT_CLAMP BIT(26) > > #define DISP_REG_OVL_ROI_BGCLR 0x0028 > > #define DISP_REG_OVL_SRC_CON 0x002c > > #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 > > * (n)) > > @@ -222,6 +225,7 @@ void mtk_ovl_layer_on(struct device *dev, > > unsigned int idx, > > unsigned int gmc_thrshd_l; > > unsigned int gmc_thrshd_h; > > unsigned int gmc_value; > > + unsigned int datapatch_con; > > struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); > > > > mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, > > @@ -237,6 +241,11 @@ void mtk_ovl_layer_on(struct device *dev, > > unsigned int idx, > > gmc_thrshd_h << 16 | gmc_thrshd_h << 24; > > mtk_ddp_write(cmdq_pkt, gmc_value, > > &ovl->cmdq_reg, ovl->regs, > > DISP_REG_OVL_RDMA_GMC(idx)); > > + > > + datapatch_con = OVL_GCLAST_EN | OVL_HDR_GCLAST_EN | > > OVL_OUTPUT_CLAMP; > > + mtk_ddp_write_mask(cmdq_pkt, datapatch_con, &ovl->cmdq_reg, > > ovl->regs, > > + DISP_REG_OVL_DATAPATH_CON, > > datapatch_con); > > For mt8173 or other SoC, this does not turn on. Now you turn on this, > would this influence other SoC? > > Regards, > CK > > > + > > mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl- > > >regs, > > DISP_REG_OVL_SRC_CON, BIT(idx)); > > } > >
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 7504e86b167a..95fd5e00eb91 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -18,14 +18,17 @@ #include "mtk_drm_ddp_comp.h" #define DISP_REG_OVL_INTEN 0x0004 -#define OVL_FME_CPL_INT BIT(1) +#define OVL_FME_CPL_INT BIT(1) #define DISP_REG_OVL_INTSTA 0x0008 #define DISP_REG_OVL_EN 0x000c #define DISP_REG_OVL_RST 0x0014 #define DISP_REG_OVL_ROI_SIZE 0x0020 #define DISP_REG_OVL_DATAPATH_CON 0x0024 -#define OVL_LAYER_SMI_ID_EN BIT(0) -#define OVL_BGCLR_SEL_IN BIT(2) +#define OVL_LAYER_SMI_ID_EN BIT(0) +#define OVL_BGCLR_SEL_IN BIT(2) +#define OVL_GCLAST_EN BIT(24) +#define OVL_HDR_GCLAST_EN BIT(25) +#define OVL_OUTPUT_CLAMP BIT(26) #define DISP_REG_OVL_ROI_BGCLR 0x0028 #define DISP_REG_OVL_SRC_CON 0x002c #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n)) @@ -222,6 +225,7 @@ void mtk_ovl_layer_on(struct device *dev, unsigned int idx, unsigned int gmc_thrshd_l; unsigned int gmc_thrshd_h; unsigned int gmc_value; + unsigned int datapatch_con; struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, @@ -237,6 +241,11 @@ void mtk_ovl_layer_on(struct device *dev, unsigned int idx, gmc_thrshd_h << 16 | gmc_thrshd_h << 24; mtk_ddp_write(cmdq_pkt, gmc_value, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx)); + + datapatch_con = OVL_GCLAST_EN | OVL_HDR_GCLAST_EN | OVL_OUTPUT_CLAMP; + mtk_ddp_write_mask(cmdq_pkt, datapatch_con, &ovl->cmdq_reg, ovl->regs, + DISP_REG_OVL_DATAPATH_CON, datapatch_con); + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_SRC_CON, BIT(idx)); }
Add datapath_con settings to support multi-layer output. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)