| Message ID | 20210709081823.18696-3-qiangqing.zhang@nxp.com (mailing list archive) |
|---|---|
| State | Deferred |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: fec: add support for i.MX8MQ and i.MX8QM | expand |
| Context | Check | Description |
|---|---|---|
| netdev/cover_letter | success | Link |
| netdev/fixes_present | success | Link |
| netdev/patch_count | success | Link |
| netdev/tree_selection | success | Clearly marked for net-next |
| netdev/subject_prefix | success | Link |
| netdev/cc_maintainers | success | CCed 6 of 6 maintainers |
| netdev/source_inline | success | Was 0 now: 0 |
| netdev/verify_signedoff | success | Link |
| netdev/module_param | success | Was 0 now: 0 |
| netdev/build_32bit | success | Errors and warnings before: 0 this patch: 0 |
| netdev/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| netdev/verify_fixes | success | Link |
| netdev/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 10 lines checked |
| netdev/build_allmodconfig_warn | success | Errors and warnings before: 0 this patch: 0 |
| netdev/header_inline | success | Link |
On Fri, Jul 09, 2021 at 04:18:20PM +0800, Joakim Zhang wrote: > From: Fugang Duan <fugang.duan@nxp.com> > > Add property for RGMII delayed clock. > > Signed-off-by: Fugang Duan <fugang.duan@nxp.com> > Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> > --- > Documentation/devicetree/bindings/net/fsl-fec.txt | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt > index 6754be1b91c4..f93b9552cfc5 100644 > --- a/Documentation/devicetree/bindings/net/fsl-fec.txt > +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt > @@ -50,6 +50,10 @@ Optional properties: > SOC internal PLL. > - "enet_out"(option), output clock for external device, like supply clock > for PHY. The clock is required if PHY clock source from SOC. > + - "enet_2x_txclk"(option), for RGMII sampleing clock which fixed at 250Mhz. > + The clock is required if SOC RGMII enable clock delay. > +- fsl,rgmii_txc_dly: add RGMII TXC delayed clock from MAC. > +- fsl,rgmii_rxc_dly: add RGMII RXC delayed clock from MAC. Don't we have standard properties for this? > > Optional subnodes: > - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes > -- > 2.17.1 > >
On Wed, Jul 14, 2021 at 05:19:37PM -0600, Rob Herring wrote: > On Fri, Jul 09, 2021 at 04:18:20PM +0800, Joakim Zhang wrote: > > From: Fugang Duan <fugang.duan@nxp.com> > > > > Add property for RGMII delayed clock. > > > > Signed-off-by: Fugang Duan <fugang.duan@nxp.com> > > Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> > > --- > > Documentation/devicetree/bindings/net/fsl-fec.txt | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt > > index 6754be1b91c4..f93b9552cfc5 100644 > > --- a/Documentation/devicetree/bindings/net/fsl-fec.txt > > +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt > > @@ -50,6 +50,10 @@ Optional properties: > > SOC internal PLL. > > - "enet_out"(option), output clock for external device, like supply clock > > for PHY. The clock is required if PHY clock source from SOC. > > + - "enet_2x_txclk"(option), for RGMII sampleing clock which fixed at 250Mhz. > > + The clock is required if SOC RGMII enable clock delay. > > +- fsl,rgmii_txc_dly: add RGMII TXC delayed clock from MAC. > > +- fsl,rgmii_rxc_dly: add RGMII RXC delayed clock from MAC. > > Don't we have standard properties for this? Yes, rx-internal-delay-ps and tx-internal-delay-ps defined in ethernet-controller.yaml Andrew
diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index 6754be1b91c4..f93b9552cfc5 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt @@ -50,6 +50,10 @@ Optional properties: SOC internal PLL. - "enet_out"(option), output clock for external device, like supply clock for PHY. The clock is required if PHY clock source from SOC. + - "enet_2x_txclk"(option), for RGMII sampleing clock which fixed at 250Mhz. + The clock is required if SOC RGMII enable clock delay. +- fsl,rgmii_txc_dly: add RGMII TXC delayed clock from MAC. +- fsl,rgmii_rxc_dly: add RGMII RXC delayed clock from MAC. Optional subnodes: - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes