| Message ID | 20210622130551.67446-1-alim.akhtar@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/2] arm64: dts: exynos7: Add cpu cache information | expand |
On 22/06/2021 15:05, Alim Akhtar wrote: > This patch adds cpu caches information to its dt > nodes so that the same is available to userspace > via sysfs. > This SoC has 48/32 KB I/D cache for each cores > and 2MB of L2 cache. > > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> > --- > Changes since v1: > * no change in this patch > * changes as per Krzysztof's review comments in patch 2/2 > > arch/arm64/boot/dts/exynos/exynos7.dtsi | 35 +++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > Thanks, patches look good. It's too late in the cycle, so I will take these after the merge window. Best regards, Krzysztof
On Tue, 22 Jun 2021 18:35:50 +0530, Alim Akhtar wrote: > This patch adds cpu caches information to its dt > nodes so that the same is available to userspace > via sysfs. > This SoC has 48/32 KB I/D cache for each cores > and 2MB of L2 cache. Applied, thanks! [1/2] arm64: dts: exynos7: Add cpu cache information commit: 43e7b8b864cc5319f323dfedf633071a434410f7 [2/2] arm64: dts: exynos5433: Add cpu cache information commit: d5c65c4aa23c52226067d7882ba2ce2055c9315d Best regards,
On 22/06/2021 15:05, Alim Akhtar wrote: > This patch adds cpu caches information to its dt > nodes so that the same is available to userspace > via sysfs. > This SoC has 48/32 KB I/D cache for each cores > and 2MB of L2 cache. > > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> > --- > Changes since v1: > * no change in this patch > * changes as per Krzysztof's review comments in patch 2/2 > > arch/arm64/boot/dts/exynos/exynos7.dtsi | 35 +++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > Thanks applied with fixes: 1. Title prefix as exynos, 2. Proper wrapping length of commit message (please use wrapping as in coding style), 3. "This patch" -> imperative mode as in coding style. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 10244e59d56d..8b06397ba6e7 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -54,6 +54,13 @@ compatible = "arm,cortex-a57"; reg = <0x0>; enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&atlas_l2>; }; cpu_atlas1: cpu@1 { @@ -61,6 +68,13 @@ compatible = "arm,cortex-a57"; reg = <0x1>; enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&atlas_l2>; }; cpu_atlas2: cpu@2 { @@ -68,6 +82,13 @@ compatible = "arm,cortex-a57"; reg = <0x2>; enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&atlas_l2>; }; cpu_atlas3: cpu@3 { @@ -75,6 +96,20 @@ compatible = "arm,cortex-a57"; reg = <0x3>; enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&atlas_l2>; + }; + + atlas_l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; }; };
This patch adds cpu caches information to its dt nodes so that the same is available to userspace via sysfs. This SoC has 48/32 KB I/D cache for each cores and 2MB of L2 cache. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> --- Changes since v1: * no change in this patch * changes as per Krzysztof's review comments in patch 2/2 arch/arm64/boot/dts/exynos/exynos7.dtsi | 35 +++++++++++++++++++++++++ 1 file changed, 35 insertions(+) base-commit: 614124bea77e452aa6df7a8714e8bc820b489922