| Message ID | 1627614864-50824-2-git-send-email-huangguangbin2@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | net: hns3: add support for TX push | expand |
On Fri, Jul 30, 2021 at 11:14:21AM +0800, Guangbin Huang wrote: > From: Xiongfeng Wang <wangxiongfeng2@huawei.com> > > DGH prohibits merging memory accesses with Normal-NC or Device-GRE > attributes before the hint instruction with any memory accesses > appearing after the hint instruction. Provide macros to expose it to the > arch code. > > Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com> > Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> > Signed-off-by: Yufeng Mo <moyufeng@huawei.com> > --- > arch/arm64/include/asm/assembler.h | 7 +++++++ > arch/arm64/include/asm/barrier.h | 1 + > 2 files changed, 8 insertions(+) > > diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h > index 89faca0e740d..5a3348b5e9f3 100644 > --- a/arch/arm64/include/asm/assembler.h > +++ b/arch/arm64/include/asm/assembler.h > @@ -90,6 +90,13 @@ > .endm > > /* > + * Data gathering hint > + */ > + .macro dgh > + hint #6 > + .endm Do we need this macro? It doesn't seem to be used anywhere.
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 89faca0e740d..5a3348b5e9f3 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -90,6 +90,13 @@ .endm /* + * Data gathering hint + */ + .macro dgh + hint #6 + .endm + +/* * RAS Error Synchronization barrier */ .macro esb diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index 451e11e5fd23..02e1735706d2 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -22,6 +22,7 @@ #define dmb(opt) asm volatile("dmb " #opt : : : "memory") #define dsb(opt) asm volatile("dsb " #opt : : : "memory") +#define dgh() asm volatile("hint #6" : : : "memory") #define psb_csync() asm volatile("hint #17" : : : "memory") #define tsb_csync() asm volatile("hint #18" : : : "memory") #define csdb() asm volatile("hint #20" : : : "memory")