| Message ID | 1627281445-12445-6-git-send-email-anshuman.khandual@arm.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64/mm: Enable FEAT_LPA2 (52 bits PA support on 4K|16K pages) | expand |
On Mon, Jul 26, 2021 at 12:07:20PM +0530, Anshuman Khandual wrote: > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index b5b13a9..1999ac6 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -934,6 +934,12 @@ config ARM64_VA_BITS > default 48 if ARM64_VA_BITS_48 > default 52 if ARM64_VA_BITS_52 > > +config ARM64_PA_BITS_52_LPA > + bool > + > +config ARM64_PA_BITS_52_LPA2 > + bool > + > choice > prompt "Physical address space size" > default ARM64_PA_BITS_48 > @@ -948,6 +954,7 @@ config ARM64_PA_BITS_52 > bool "52-bit (ARMv8.2)" > depends on ARM64_64K_PAGES > depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN > + select ARM64_PA_BITS_52_LPA if ARM64_64K_PAGES > help > Enable support for a 52-bit physical address space, introduced as > part of the ARMv8.2-LPA extension. Do we actually need to bother with LPA, LPA2 options? We could just add an extra defined(ARM64_64K_PAGES) in places, it may be easier to follow in a few years time when we won't remember what LPA or LPA2 was. I haven't got to the rest of the patches but it may just be simpler to define the shifts separately for 52-bit based on 4K/16K/64K and ignore the LPA/LPA2 distinction altogether (we'll still keep it for CPUID checking though).
On 8/5/21 10:55 PM, Catalin Marinas wrote: > On Mon, Jul 26, 2021 at 12:07:20PM +0530, Anshuman Khandual wrote: >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index b5b13a9..1999ac6 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -934,6 +934,12 @@ config ARM64_VA_BITS >> default 48 if ARM64_VA_BITS_48 >> default 52 if ARM64_VA_BITS_52 >> >> +config ARM64_PA_BITS_52_LPA >> + bool >> + >> +config ARM64_PA_BITS_52_LPA2 >> + bool >> + >> choice >> prompt "Physical address space size" >> default ARM64_PA_BITS_48 >> @@ -948,6 +954,7 @@ config ARM64_PA_BITS_52 >> bool "52-bit (ARMv8.2)" >> depends on ARM64_64K_PAGES >> depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN >> + select ARM64_PA_BITS_52_LPA if ARM64_64K_PAGES >> help >> Enable support for a 52-bit physical address space, introduced as >> part of the ARMv8.2-LPA extension. > > Do we actually need to bother with LPA, LPA2 options? We could just add These are internal configs for code organization purpose, which otherwise becomes bit entangled. Basically these configs just imply the following combinations being selected together. - ARM64_PA_BITS_52_LPA : ARM64_64K_PAGES && ARM64_PA_BITS_52 - ARM64_PA_BITS_52_LPA2 : (ARM64_4K_PAGES || ARM64_16K_PAGES) && ARM64_PA_BITS_52 There are some benefits here - ARM64_PA_BITS_52_[LPA|LPA2] helps in avoiding writing out code blocks for these above combinations in various different places, keeps it clean. - Cleanly encapsulates ARM64_PA_BITS_52 implementation into two different logical code blocks depending on the respective HW features enabling it i.e FEAT_LPA and FEAT_LPA2. This is important because there are distinct pte <----> phys encodings, ptdump handling, setting TCR_DS, FEAT_LPA2 detection, PTE sharability attribute handling which are dependent on how 52 bits PA is implemented. > an extra defined(ARM64_64K_PAGES) in places, it may be easier to follow > in a few years time when we won't remember what LPA or LPA2 was. I Are you suggesting that over the years, folks might forget about LPA/LPA2 details and might have to look back in arch/arm64/Kconfig to figure this out, which is not desirable ? But would not that be an acceptable trade off given the encapsulation it helps achieve ? > haven't got to the rest of the patches but it may just be simpler to > define the shifts separately for 52-bit based on 4K/16K/64K and ignore > the LPA/LPA2 distinction altogether (we'll still keep it for CPUID > checking though). > Sure. After you have gone through and reviewed rest of the series, if it still appears that dropping LPA/LPA2 distinction here would be simpler from a long term perspective, will be happy to change it accordingly.
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b5b13a9..1999ac6 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -934,6 +934,12 @@ config ARM64_VA_BITS default 48 if ARM64_VA_BITS_48 default 52 if ARM64_VA_BITS_52 +config ARM64_PA_BITS_52_LPA + bool + +config ARM64_PA_BITS_52_LPA2 + bool + choice prompt "Physical address space size" default ARM64_PA_BITS_48 @@ -948,6 +954,7 @@ config ARM64_PA_BITS_52 bool "52-bit (ARMv8.2)" depends on ARM64_64K_PAGES depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN + select ARM64_PA_BITS_52_LPA if ARM64_64K_PAGES help Enable support for a 52-bit physical address space, introduced as part of the ARMv8.2-LPA extension. diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 89faca0..fedc202 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -607,26 +607,26 @@ alternative_endif .endm .macro phys_to_pte, pte, phys -#ifdef CONFIG_ARM64_PA_BITS_52 +#ifdef CONFIG_ARM64_PA_BITS_52_LPA /* * We assume \phys is 64K aligned and this is guaranteed by only * supporting this configuration with 64K pages. */ orr \pte, \phys, \phys, lsr #36 and \pte, \pte, #PTE_ADDR_MASK -#else +#else /* !CONFIG_ARM64_PA_BITS_52_LPA */ mov \pte, \phys -#endif +#endif /* CONFIG_ARM64_PA_BITS_52_LPA */ .endm .macro pte_to_phys, phys, pte -#ifdef CONFIG_ARM64_PA_BITS_52 +#ifdef CONFIG_ARM64_PA_BITS_52_LPA ubfiz \phys, \pte, #(48 - 16 - 12), #16 bfxil \phys, \pte, #16, #32 lsl \phys, \phys, #16 -#else +#else /* !CONFIG_ARM64_PA_BITS_52_LPA */ and \phys, \pte, #PTE_ADDR_MASK -#endif +#endif /* CONFIG_ARM64_PA_BITS_52_LPA */ .endm /* diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index 1eb5574..f375bcf 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -155,13 +155,14 @@ #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ +#ifdef CONFIG_ARM64_PA_BITS_52_LPA #define PTE_ADDR_LOW (((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT) -#ifdef CONFIG_ARM64_PA_BITS_52 #define PTE_ADDR_HIGH (_AT(pteval_t, 0xf) << 12) #define PTE_ADDR_MASK (PTE_ADDR_LOW | PTE_ADDR_HIGH) -#else +#else /* !CONFIG_ARM64_PA_BITS_52_LPA */ +#define PTE_ADDR_LOW (((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT) #define PTE_ADDR_MASK PTE_ADDR_LOW -#endif +#endif /* CONFIG_ARM64_PA_BITS_52_LPA */ /* * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index f09bf5c..3c57fb2 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -66,14 +66,14 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; * Macros to convert between a physical address and its placement in a * page table entry, taking care of 52-bit addresses. */ -#ifdef CONFIG_ARM64_PA_BITS_52 +#ifdef CONFIG_ARM64_PA_BITS_52_LPA #define __pte_to_phys(pte) \ ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) -#else +#else /* !CONFIG_ARM64_PA_BITS_52_LPA */ #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) #define __phys_to_pte_val(phys) (phys) -#endif +#endif /* CONFIG_ARM64_PA_BITS_52_LPA */ #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) #define pfn_pte(pfn,prot) \ diff --git a/arch/arm64/mm/pgd.c b/arch/arm64/mm/pgd.c index 4a64089..090dfbe 100644 --- a/arch/arm64/mm/pgd.c +++ b/arch/arm64/mm/pgd.c @@ -40,7 +40,7 @@ void __init pgtable_cache_init(void) if (PGD_SIZE == PAGE_SIZE) return; -#ifdef CONFIG_ARM64_PA_BITS_52 +#ifdef CONFIG_ARM64_PA_BITS_52_LPA /* * With 52-bit physical addresses, the architecture requires the * top-level table to be aligned to at least 64 bytes.
Going forward, CONFIG_ARM64_PA_BITS_52 could be enabled on a system via two different architecture features i.e FEAT_LPA for CONFIG_ARM64_64K_PAGES and FEAT_LPA2 for CONFIG_ARM64_[4K|16K]_PAGES. But CONFIG_ARM64_PA_BITS_52 is exclussively available on 64K page size config currently, which needs to be freed up for other page size configs to use when FEAT_LPA2 gets enabled. To achieve CONFIG_ARM64_PA_BITS_52 and CONFIG_ARM64_64K_PAGES decoupling, and also to reduce #ifdefs while navigating various page size configs, this adds two internal config options CONFIG_ARM64_PA_BITS_52_[LPA|LPA2]. While here it also converts existing 64K page size based FEAT_LPA implementations to use CONFIG_ARM64_PA_BITS_52_LPA. TTBR representation remains same for both FEAT_LPA and FEAT_LPA2. No functional change for 64K page size config. Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- arch/arm64/Kconfig | 7 +++++++ arch/arm64/include/asm/assembler.h | 12 ++++++------ arch/arm64/include/asm/pgtable-hwdef.h | 7 ++++--- arch/arm64/include/asm/pgtable.h | 6 +++--- arch/arm64/mm/pgd.c | 2 +- 5 files changed, 21 insertions(+), 13 deletions(-)