| Message ID | 20210817012754.8710-23-digetx@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | NVIDIA Tegra power management patches for 5.16 | expand |
On Tue, Aug 17, 2021 at 04:27:42AM +0300, Dmitry Osipenko wrote: > The SPI on Tegra belongs to the core power domain and we're going to > enable GENPD support for the core domain. Now SPI driver must use OPP > API for driving the controller's clock rate because OPP API takes care > of reconfiguring the domain's performance state in accordance to the > rate. Add OPP support to the driver. Acked-by: Mark Brown <broonie@kernel.org> Is there a concrete dependency here or can I merge this separately?
17.08.2021 15:22, Mark Brown пишет: > On Tue, Aug 17, 2021 at 04:27:42AM +0300, Dmitry Osipenko wrote: >> The SPI on Tegra belongs to the core power domain and we're going to >> enable GENPD support for the core domain. Now SPI driver must use OPP >> API for driving the controller's clock rate because OPP API takes care >> of reconfiguring the domain's performance state in accordance to the >> rate. Add OPP support to the driver. > > Acked-by: Mark Brown <broonie@kernel.org> > > Is there a concrete dependency here or can I merge this separately? This patch depends on the new OPP helpers added earlier in this series. In particular it depends on these patches: opp: Add dev_pm_opp_sync() helper soc/tegra: Add devm_tegra_core_dev_init_opp_table_simple() Thank you for the ack!
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c index deff16ba6d58..37cb15dc59f7 100644 --- a/drivers/spi/spi-tegra20-slink.c +++ b/drivers/spi/spi-tegra20-slink.c @@ -18,12 +18,15 @@ #include <linux/kthread.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_opp.h> #include <linux/pm_runtime.h> #include <linux/of.h> #include <linux/of_device.h> #include <linux/reset.h> #include <linux/spi/spi.h> +#include <soc/tegra/common.h> + #define SLINK_COMMAND 0x000 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5) @@ -683,7 +686,7 @@ static int tegra_slink_start_transfer_one(struct spi_device *spi, bits_per_word = t->bits_per_word; speed = t->speed_hz; if (speed != tspi->cur_speed) { - clk_set_rate(tspi->clk, speed * 4); + dev_pm_opp_set_rate(tspi->dev, speed * 4); tspi->cur_speed = speed; } @@ -1054,6 +1057,10 @@ static int tegra_slink_probe(struct platform_device *pdev) goto exit_free_master; } + ret = devm_tegra_core_dev_init_opp_table_simple(&pdev->dev); + if (ret) + return ret; + /* disabled clock may cause interrupt storm upon request */ tspi->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(tspi->clk)) { @@ -1205,6 +1212,12 @@ static int tegra_slink_runtime_resume(struct device *dev) struct tegra_slink_data *tspi = spi_master_get_devdata(master); int ret; + ret = dev_pm_opp_sync(dev); + if (ret) { + dev_err(dev, "failed to sync OPP: %d\n", ret); + return ret; + } + ret = clk_prepare_enable(tspi->clk); if (ret < 0) { dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
The SPI on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now SPI driver must use OPP API for driving the controller's clock rate because OPP API takes care of reconfiguring the domain's performance state in accordance to the rate. Add OPP support to the driver. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/spi/spi-tegra20-slink.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)