| Message ID | 20210817012754.8710-10-digetx@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | NVIDIA Tegra power management patches for 5.16 | expand |
On Tue, Aug 17, 2021 at 04:27:29AM +0300, Dmitry Osipenko wrote: > Memory Client should be blocked before hardware reset is asserted in order > to prevent memory corruption and hanging of memory controller. > > Document Memory Client resets of Host1x, GR2D and GR3D hardware units. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > .../bindings/display/tegra/nvidia,tegra20-host1x.txt | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt > index 62861a8fb5c6..07a08653798b 100644 > --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt > @@ -18,6 +18,7 @@ Required properties: > - resets: Must contain an entry for each entry in reset-names. > See ../reset/reset.txt for details. > - reset-names: Must include the following entries: > + - mc > - host1x New entries should be at the end. Order matters. > > Optional properties: > @@ -197,6 +198,7 @@ of the following host1x client modules: > - resets: Must contain an entry for each entry in reset-names. > See ../reset/reset.txt for details. > - reset-names: Must include the following entries: > + - mc > - 2d > > Optional properties: > @@ -222,6 +224,8 @@ of the following host1x client modules: > - resets: Must contain an entry for each entry in reset-names. > See ../reset/reset.txt for details. > - reset-names: Must include the following entries: > + - mc > + - mc2 (Only required on SoCs with two 3D clocks) > - 3d > - 3d2 (Only required on SoCs with two 3D clocks) > > -- > 2.32.0 > >
18.08.2021 04:16, Rob Herring пишет: > On Tue, Aug 17, 2021 at 04:27:29AM +0300, Dmitry Osipenko wrote: >> Memory Client should be blocked before hardware reset is asserted in order >> to prevent memory corruption and hanging of memory controller. >> >> Document Memory Client resets of Host1x, GR2D and GR3D hardware units. >> >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> >> --- >> .../bindings/display/tegra/nvidia,tegra20-host1x.txt | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt >> index 62861a8fb5c6..07a08653798b 100644 >> --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt >> +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt >> @@ -18,6 +18,7 @@ Required properties: >> - resets: Must contain an entry for each entry in reset-names. >> See ../reset/reset.txt for details. >> - reset-names: Must include the following entries: >> + - mc >> - host1x > > New entries should be at the end. Order matters. Indeed, order matters. In this case it matters by the hardware because memory reset must be asserted before the controller's reset. We rely on it in the code of the GENPD driver. Hence it's the intended order in this patch.
18.08.2021 04:37, Dmitry Osipenko пишет: > 18.08.2021 04:16, Rob Herring пишет: >> On Tue, Aug 17, 2021 at 04:27:29AM +0300, Dmitry Osipenko wrote: >>> Memory Client should be blocked before hardware reset is asserted in order >>> to prevent memory corruption and hanging of memory controller. >>> >>> Document Memory Client resets of Host1x, GR2D and GR3D hardware units. >>> >>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> >>> --- >>> .../bindings/display/tegra/nvidia,tegra20-host1x.txt | 4 ++++ >>> 1 file changed, 4 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt >>> index 62861a8fb5c6..07a08653798b 100644 >>> --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt >>> +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt >>> @@ -18,6 +18,7 @@ Required properties: >>> - resets: Must contain an entry for each entry in reset-names. >>> See ../reset/reset.txt for details. >>> - reset-names: Must include the following entries: >>> + - mc >>> - host1x >> >> New entries should be at the end. Order matters. > > Indeed, order matters. In this case it matters by the hardware because > memory reset must be asserted before the controller's reset. We rely on > it in the code of the GENPD driver. Hence it's the intended order in > this patch. > Although, my bad. It should be to reorder items here, it's not a GENPD binding.
18.08.2021 05:04, Dmitry Osipenko пишет: > 18.08.2021 04:37, Dmitry Osipenko пишет: >> 18.08.2021 04:16, Rob Herring пишет: >>> On Tue, Aug 17, 2021 at 04:27:29AM +0300, Dmitry Osipenko wrote: >>>> Memory Client should be blocked before hardware reset is asserted in order >>>> to prevent memory corruption and hanging of memory controller. >>>> >>>> Document Memory Client resets of Host1x, GR2D and GR3D hardware units. >>>> >>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> >>>> --- >>>> .../bindings/display/tegra/nvidia,tegra20-host1x.txt | 4 ++++ >>>> 1 file changed, 4 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt >>>> index 62861a8fb5c6..07a08653798b 100644 >>>> --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt >>>> +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt >>>> @@ -18,6 +18,7 @@ Required properties: >>>> - resets: Must contain an entry for each entry in reset-names. >>>> See ../reset/reset.txt for details. >>>> - reset-names: Must include the following entries: >>>> + - mc >>>> - host1x >>> >>> New entries should be at the end. Order matters. >> >> Indeed, order matters. In this case it matters by the hardware because >> memory reset must be asserted before the controller's reset. We rely on >> it in the code of the GENPD driver. Hence it's the intended order in >> this patch. >> > > Although, my bad. It should be to reorder items here, it's not a GENPD > binding. > * should be fine I'll change it in v9.
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 62861a8fb5c6..07a08653798b 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -18,6 +18,7 @@ Required properties: - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: + - mc - host1x Optional properties: @@ -197,6 +198,7 @@ of the following host1x client modules: - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: + - mc - 2d Optional properties: @@ -222,6 +224,8 @@ of the following host1x client modules: - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: + - mc + - mc2 (Only required on SoCs with two 3D clocks) - 3d - 3d2 (Only required on SoCs with two 3D clocks)
Memory Client should be blocked before hardware reset is asserted in order to prevent memory corruption and hanging of memory controller. Document Memory Client resets of Host1x, GR2D and GR3D hardware units. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- .../bindings/display/tegra/nvidia,tegra20-host1x.txt | 4 ++++ 1 file changed, 4 insertions(+)