| Message ID | 20210820133829.1.Ica46f428de8c3beb600760dbcd63cf879ec24baf@changeid (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: rockchip: add RK3399 Gru gpio-line-names | expand |
Hi, On Fri, Aug 20, 2021 at 1:38 PM Brian Norris <briannorris@chromium.org> wrote: > > It's convenient to get nice names for GPIOs. In particular, Chrome OS > tooling looks for "AP_FLASH_WP" and "AP_FLASH_WP_L". The rest are > provided for convenience. > > Gru-Bob and Gru-Kevin share the gru-chromebook.dtsi, and for the most > part they share pin meanings. I omitted a few areas where components > were available only on one or the other. > > Signed-off-by: Brian Norris <briannorris@chromium.org> > --- > > .../dts/rockchip/rk3399-gru-chromebook.dtsi | 176 +++++++++++++++++ > .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 180 ++++++++++++++++++ > 2 files changed, 356 insertions(+) I didn't walk through the schematics and double-check the rails personally, but the idea here is right. This matches the type of thing we did for veyron, like in commit ca3516b32cd9 ("ARM: dts: rockchip: Add pin names for rk3288-veyron-minnie") I guess one minor nit (now that I look back on the veyron patch where I mentioned it explicitly in the commit message) is that on the veyron ones we sorted this down at the bottom with the other pinctrl stuff instead of sorting it alphabetically with everything else. I'll let Heiko say which he likes better. I also notice for veyron that we had a second "ABI" exception for the recovery mode pin, but I believe that goes through a different mechanism now so we're good there. Even though I didn't do a line-by-line review, I'll still give: Reviewed-by: Douglas Anderson <dianders@chromium.org> ...though it's possible an "Acked-by" would be more in the spirit of that? Not sure... -Doug
On Fri, Aug 20, 2021 at 2:05 PM Doug Anderson <dianders@chromium.org> wrote: > I guess one minor nit (now that I look back on the veyron patch where > I mentioned it explicitly in the commit message) is that on the veyron > ones we sorted this down at the bottom with the other pinctrl stuff > instead of sorting it alphabetically with everything else. I'll let > Heiko say which he likes better. Huh, didn't notice that semi-convention. I can sort it however Heiko prefers. > I also notice for veyron that we had a second "ABI" exception for the > recovery mode pin, but I believe that goes through a different > mechanism now so we're good there. I believe the recovery mode pin is dropped from recent designs (don't quote me in general on that), and there's a different mechanism used just to get the at-boot-time "recovery mode" state directly from the firmware. > Even though I didn't do a line-by-line review, I'll still give: > > Reviewed-by: Douglas Anderson <dianders@chromium.org> > > ...though it's possible an "Acked-by" would be more in the spirit of > that? Not sure... Thanks! Brian
Am Freitag, 20. August 2021, 23:16:23 CEST schrieb Brian Norris: > On Fri, Aug 20, 2021 at 2:05 PM Doug Anderson <dianders@chromium.org> wrote: > > I guess one minor nit (now that I look back on the veyron patch where > > I mentioned it explicitly in the commit message) is that on the veyron > > ones we sorted this down at the bottom with the other pinctrl stuff > > instead of sorting it alphabetically with everything else. I'll let > > Heiko say which he likes better. > > Huh, didn't notice that semi-convention. I can sort it however Heiko prefers. Hmm, I wouldn't call it a semi-convention ... it was more an idea of getting all the longer pages of "stuff" out of the way. I don't think I have a real hard preference for the gpioX nodes and I guess in the long run it might be helpful to try to limit the number of "semi-conventions" . I still like "pinctrl at the bottom", but I guess it might be easier to with alphabetical for nodes with the rest :-) . Heiko > > I also notice for veyron that we had a second "ABI" exception for the > > recovery mode pin, but I believe that goes through a different > > mechanism now so we're good there. > > I believe the recovery mode pin is dropped from recent designs (don't > quote me in general on that), and there's a different mechanism used > just to get the at-boot-time "recovery mode" state directly from the > firmware. > > > Even though I didn't do a line-by-line review, I'll still give: > > > > Reviewed-by: Douglas Anderson <dianders@chromium.org> > > > > ...though it's possible an "Acked-by" would be more in the spirit of > > that? Not sure... > > Thanks! > > Brian >
On Fri, 20 Aug 2021 13:38:35 -0700, Brian Norris wrote: > It's convenient to get nice names for GPIOs. In particular, Chrome OS > tooling looks for "AP_FLASH_WP" and "AP_FLASH_WP_L". The rest are > provided for convenience. > > Gru-Bob and Gru-Kevin share the gru-chromebook.dtsi, and for the most > part they share pin meanings. I omitted a few areas where components > were available only on one or the other. Applied, thanks! [1/1] arm64: dts: rockchip: add RK3399 Gru gpio-line-names commit: 9a35fd01f4abc3974e12539448038307acf27f16 Best regards,
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 1384dabbdf40..9b2c679f5eca 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -251,6 +251,182 @@ edp_out_panel: endpoint@0 { }; }; +&gpio0 { + gpio-line-names = /* GPIO0 A 0-7 */ + "AP_RTC_CLK_IN", + "EC_AP_INT_L", + "PP1800_AUDIO_EN", + "BT_HOST_WAKE_L", + "WLAN_MODULE_PD_L", + "H1_INT_OD_L", + "CENTERLOGIC_DVS_PWM", + "", + + /* GPIO0 B 0-4 */ + "WIFI_HOST_WAKE_L", + "PMUIO2_33_18_L", + "PP1500_EN", + "AP_EC_WARM_RESET_REQ", + "PP3000_EN"; +}; + +&gpio1 { + gpio-line-names = /* GPIO1 A 0-7 */ + "", + "", + "SPK_PA_EN", + "", + "TRACKPAD_INT_L", + "AP_EC_S3_S0_L", + "AP_EC_OVERTEMP", + "AP_SPI_FLASH_MISO", + + /* GPIO1 B 0-7 */ + "AP_SPI_FLASH_MOSI_R", + "AP_SPI_FLASH_CLK_R", + "AP_SPI_FLASH_CS_L_R", + "WLAN_MODULE_RESET_L", + "WIFI_DISABLE_L", + "MIC_INT", + "", + "AP_I2C_DVS_SDA", + + /* GPIO1 C 0-7 */ + "AP_I2C_DVS_SCL", + "AP_BL_EN", + /* + * AP_FLASH_WP is crossystem ABI. Schematics call it + * AP_FW_WP or CPU1_FW_WP, depending on the variant. + */ + "AP_FLASH_WP", + "LITCPU_DVS_PWM", + "AP_I2C_AUDIO_SDA", + "AP_I2C_AUDIO_SCL", + "", + "HEADSET_INT_L"; +}; + +&gpio2 { + gpio-line-names = /* GPIO2 A 0-7 */ + "", + "", + "SD_IO_PWR_EN", + "", + "", + "", + "", + "", + + /* GPIO2 B 0-7 */ + "", + "", + "", + "", + "", + "", + "", + "", + + /* GPIO2 C 0-7 */ + "", + "", + "", + "", + "AP_SPI_EC_MISO", + "AP_SPI_EC_MOSI", + "AP_SPI_EC_CLK", + "AP_SPI_EC_CS_L", + + /* GPIO2 D 0-4 */ + "BT_DEV_WAKE_L", + "", + "WIFI_PCIE_CLKREQ_L", + "WIFI_PERST_L", + "SD_PWR_3000_1800_L"; +}; + +&gpio3 { + gpio-line-names = /* GPIO3 A 0-7 */ + "", + "", + "", + "", + "AP_SPI_TPM_MISO", + "AP_SPI_TPM_MOSI_R", + "AP_SPI_TPM_CLK_R", + "AP_SPI_TPM_CS_L_R", + + /* GPIO3 B 0-7 */ + "EC_IN_RW", + "", + "AP_I2C_TP_SDA", + "AP_I2C_TP_SCL", + "AP_I2C_TP_PU_EN", + "TOUCH_INT_L", + "", + "", + + /* GPIO3 C 0-7 */ + "", + "", + "", + "", + "", + "", + "", + "", + + /* GPIO3 D 0-7 */ + "I2S0_SCLK", + "I2S0_LRCK_RX", + "I2S0_LRCK_TX", + "I2S0_SDI_0", + "I2S0_SDI_1", + "", + "I2S0_SDO_1", + "I2S0_SDO_0"; +}; + +&gpio4 { + gpio-line-names = /* GPIO4 A 0-7 */ + "I2S_MCLK", + "AP_I2C_MIC_SDA", + "AP_I2C_MIC_SCL", + "", + "", + "", + "", + "", + + /* GPIO4 B 0-7 */ + "", + "", + "", + "", + "", + "", + "", + "", + + /* GPIO4 C 0-7 */ + "AP_I2C_TS_SDA", + "AP_I2C_TS_SCL", + "GPU_DVS_PWM", + "UART_DBG_TX_AP_RX", + "UART_AP_TX_DBG_RX", + "", + "BIGCPU_DVS_PWM", + "EDP_HPD_3V0", + + /* GPIO4 D 0-5 */ + "SD_CARD_DET_L", + "USB_DP_HPD", + "TOUCH_RESET_L", + "PP3300_DISP_EN", + "", + "SD_SLOT_PWR_EN"; +}; + ap_i2c_mic: &i2c1 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index 5d7a9d96d163..61afb5f0f15b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -389,6 +389,186 @@ &cru { <400000000>; }; +&gpio0 { + gpio-line-names = /* GPIO0 A 0-7 */ + "CLK_32K_AP", + "EC_IN_RW_OD", + "SPK_PA_EN", + "WLAN_PERST_1V8_L", + "WLAN_PD_1V8_L", + "WLAN_RF_KILL_1V8_L", + "BIGCPU_DVS_PWM", + "SD_CD_L_JTAG_EN", + + /* GPIO0 B 0-5 */ + "BT_EN_BT_RF_KILL_1V8_L", + "PMUIO2_33_18_L_PP3300_S0_EN", + "TOUCH_RESET_L", + "AP_EC_WARM_RESET_REQ", + "PEN_RESET_L", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics call + * it AP_FLASH_WP_R_ODL. + */ + "AP_FLASH_WP_L"; +}; + +&gpio1 { + gpio-line-names = /* GPIO1 A 0-7 */ + "PEN_INT_ODL", + "PEN_EJECT_ODL", + "BT_HOST_WAKE_1V8_L", + "WLAN_HOST_WAKE_1V8_L", + "TOUCH_INT_ODL", + "AP_EC_S3_S0_L", + "AP_EC_OVERTEMP", + "AP_SPI_FLASH_MISO", + + /* GPIO1 B 0-7 */ + "AP_SPI_FLASH_MOSI_R", + "AP_SPI_FLASH_CLK_R", + "AP_SPI_FLASH_CS_L_R", + "SD_CARD_DET_ODL", + "", + "AP_EXPANSION_IO1", + "AP_EXPANSION_IO2", + "AP_I2C_DISP_SDA", + + /* GPIO1 C 0-7 */ + "AP_I2C_DISP_SCL", + "H1_INT_ODL", + "EC_AP_INT_ODL", + "LITCPU_DVS_PWM", + "AP_I2C_AUDIO_SDA", + "AP_I2C_AUDIO_SCL", + "AP_EXPANSION_IO3", + "HEADSET_INT_ODL", + + /* GPIO1 D0 */ + "AP_EXPANSION_IO4"; +}; + +&gpio2 { + gpio-line-names = /* GPIO2 A 0-7 */ + "AP_I2C_PEN_SDA", + "AP_I2C_PEN_SCL", + "SD_IO_PWR_EN", + "UCAM_RST_L", + "PP1250_CAM_EN", + "WCAM_RST_L", + "AP_EXPANSION_IO5", + "AP_I2C_CAM_SDA", + + /* GPIO2 B 0-7 */ + "AP_I2C_CAM_SCL", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "", + "", + "", + + /* GPIO2 C 0-7 */ + "UART_EXPANSION_TX_AP_RX", + "UART_AP_TX_EXPANSION_RX", + "UART_EXPANSION_RTS_AP_CTS", + "UART_AP_RTS_EXPANSION_CTS", + "AP_SPI_EC_MISO", + "AP_SPI_EC_MOSI", + "AP_SPI_EC_CLK", + "AP_SPI_EC_CS_L", + + /* GPIO2 D 0-4 */ + "PP2800_CAM_EN", + "CLK_24M_CAM", + "WLAN_PCIE_CLKREQ_1V8_L", + "", + "SD_PWR_3000_1800_L"; +}; + +&gpio3 { + gpio-line-names = /* GPIO3 A 0-7 */ + "", + "", + "", + "", + "", + "", + "", + "", + + /* GPIO3 B 0-7 */ + "", + "", + "", + "", + "", + "", + "", + "", + + /* GPIO3 C 0-7 */ + "", + "", + "", + "", + "", + "", + "", + "", + + /* GPIO3 D 0-7 */ + "I2S0_SCLK", + "I2S0_LRCK_RX", + "I2S0_LRCK_TX", + "I2S0_SDI_0", + "STRAP_LCDBIAS_L", + "STRAP_FEATURE_1", + "STRAP_FEATURE_2", + "I2S0_SDO_0"; +}; + +&gpio4 { + gpio-line-names = /* GPIO4 A 0-7 */ + "I2S_MCLK", + "AP_I2C_EXPANSION_SDA", + "AP_I2C_EXPANSION_SCL", + "DMIC_EN", + "", + "", + "", + "", + + /* GPIO4 B 0-7 */ + "", + "", + "", + "", + "", + "", + "", + "", + + /* GPIO4 C 0-7 */ + "AP_I2C_TS_SDA", + "AP_I2C_TS_SCL", + "GPU_DVS_PWM", + "UART_DBG_TX_AP_RX", + "UART_AP_TX_DBG_RX", + "BL_EN", + "BL_PWM", + "", + + /* GPIO4 D 0-5 */ + "", + "DISPLAY_RST_L", + "", + "PPVARP_LCD_EN", + "PPVARN_LCD_EN", + "SD_SLOT_PWR_EN"; +}; + &i2c_tunnel { google,remote-bus = <0>; };
It's convenient to get nice names for GPIOs. In particular, Chrome OS tooling looks for "AP_FLASH_WP" and "AP_FLASH_WP_L". The rest are provided for convenience. Gru-Bob and Gru-Kevin share the gru-chromebook.dtsi, and for the most part they share pin meanings. I omitted a few areas where components were available only on one or the other. Signed-off-by: Brian Norris <briannorris@chromium.org> --- .../dts/rockchip/rk3399-gru-chromebook.dtsi | 176 +++++++++++++++++ .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 180 ++++++++++++++++++ 2 files changed, 356 insertions(+)