| Message ID | 20210819070954.16679-5-moudy.ho@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | media: mediatek: support mdp3 on mt8183 platform | expand |
Hi, Moudy: On Thu, 2021-08-19 at 15:09 +0800, Moudy Ho wrote: > Add device nodes for Media Data Path 3 (MDP3) modules. > > Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com> > Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 110 +++++++++++++++++++++++ > 1 file changed, 110 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index f90df6439c08..7cb1fcfeefb6 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -1232,6 +1232,108 @@ > mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; > }; > > + mdp3_rdma0: mdp3_rdma0@14001000 { > + compatible = "mediatek,mt8183-mdp3", > + "mediatek,mt8183-mdp3-rdma"; > + mediatek,scp = <&scp>; > + mediatek,mdp3-id = <0>; > + mdp3-comps = "mediatek,mt8183-mdp3-dl1", "mediatek,mt8183-mdp3-dl2", > + "mediatek,mt8183-mdp3-path1", "mediatek,mt8183-mdp3-path2", > + "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-mdp3-exto"; > + mdp3-comp-ids = <0 1 0 1 0 1>; > + reg = <0 0x14001000 0 0x1000>, > + <0 0x14000000 0 0x1000>, > + <0 0x14005000 0 0x1000>, > + <0 0x14006000 0 0x1000>, > + <0 0x15020000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>, > + <&gce SUBSYS_1400XXXX 0 0x1000>, > + <&gce SUBSYS_1400XXXX 0x5000 0x1000>, > + <&gce SUBSYS_1400XXXX 0x6000 0x1000>, > + <&gce SUBSYS_1502XXXX 0 0x1000>; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_MDP_RDMA0>, > + <&mmsys CLK_MM_MDP_RSZ1>, > + <&mmsys CLK_MM_MDP_DL_TXCK>, > + <&mmsys CLK_MM_MDP_DL_RX>, > + <&mmsys CLK_MM_IPU_DL_TXCK>, > + <&mmsys CLK_MM_IPU_DL_RX>; > + iommus = <&iommu M4U_PORT_MDP_RDMA0>; > + mediatek,mmsys = <&mmsys>; > + mediatek,mm-mutex = <&mutex>; > + mediatek,mailbox-gce = <&gce>; > + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, > + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>, > + <&gce 22 CMDQ_THR_PRIO_LOWEST 0>, > + <&gce 23 CMDQ_THR_PRIO_LOWEST 0>; > + gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>, > + <&gce 0x14010000 SUBSYS_1401XXXX>, > + <&gce 0x14020000 SUBSYS_1402XXXX>, > + <&gce 0x15020000 SUBSYS_1502XXXX>; > + mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, > + <CMDQ_EVENT_MDP_RDMA0_EOF>, > + <CMDQ_EVENT_MDP_RSZ0_SOF>, CMDQ_EVENT_MDP_RSZ0_SOF is sent from rsz0 to gce, so move this event to rsz0. Regards, CK > + <CMDQ_EVENT_MDP_RSZ1_SOF>, > + <CMDQ_EVENT_MDP_TDSHP_SOF>, > + <CMDQ_EVENT_MDP_WROT0_SOF>, > + <CMDQ_EVENT_MDP_WROT0_EOF>, > + <CMDQ_EVENT_MDP_WDMA0_SOF>, > + <CMDQ_EVENT_MDP_WDMA0_EOF>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>, > + <CMDQ_EVENT_WPE_A_DONE>, > + <CMDQ_EVENT_SPE_B_DONE>; > + }; > + > + mdp3_rsz0: mdp3_rsz0@14003000 { > + compatible = "mediatek,mt8183-mdp3-rsz"; > + mediatek,mdp3-id = <0>; > + reg = <0 0x14003000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_RSZ0>; > + }; > + > + mdp3_rsz1: mdp3_rsz1@14004000 { > + compatible = "mediatek,mt8183-mdp3-rsz"; > + mediatek,mdp3-id = <1>; > + reg = <0 0x14004000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_RSZ1>; > + }; > + > + mdp3_wrot0: mdp3_wrot0@14005000 { > + compatible = "mediatek,mt8183-mdp3-wrot"; > + mediatek,mdp3-id = <0>; > + reg = <0 0x14005000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_MDP_WROT0>; > + iommus = <&iommu M4U_PORT_MDP_WROT0>; > + }; > + > + mdp3_wdma: mdp3_wdma@14006000 { > + compatible = "mediatek,mt8183-mdp3-wdma"; > + mediatek,mdp3-id = <0>; > + reg = <0 0x14006000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_MDP_WDMA0>; > + iommus = <&iommu M4U_PORT_MDP_WDMA0>; > + }; > + > ovl0: ovl@14008000 { > compatible = "mediatek,mt8183-disp-ovl"; > reg = <0 0x14008000 0 0x1000>; > @@ -1378,6 +1480,14 @@ > power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > }; > > + mdp3_ccorr: mdp3_ccorr@1401c000 { > + compatible = "mediatek,mt8183-mdp3-ccorr"; > + mediatek,mdp3-id = <0>; > + reg = <0 0x1401c000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_CCORR>; > + }; > + > imgsys: syscon@15020000 { > compatible = "mediatek,mt8183-imgsys", "syscon"; > reg = <0 0x15020000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index f90df6439c08..7cb1fcfeefb6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1232,6 +1232,108 @@ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; + mdp3_rdma0: mdp3_rdma0@14001000 { + compatible = "mediatek,mt8183-mdp3", + "mediatek,mt8183-mdp3-rdma"; + mediatek,scp = <&scp>; + mediatek,mdp3-id = <0>; + mdp3-comps = "mediatek,mt8183-mdp3-dl1", "mediatek,mt8183-mdp3-dl2", + "mediatek,mt8183-mdp3-path1", "mediatek,mt8183-mdp3-path2", + "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-mdp3-exto"; + mdp3-comp-ids = <0 1 0 1 0 1>; + reg = <0 0x14001000 0 0x1000>, + <0 0x14000000 0 0x1000>, + <0 0x14005000 0 0x1000>, + <0 0x14006000 0 0x1000>, + <0 0x15020000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>, + <&gce SUBSYS_1400XXXX 0 0x1000>, + <&gce SUBSYS_1400XXXX 0x5000 0x1000>, + <&gce SUBSYS_1400XXXX 0x6000 0x1000>, + <&gce SUBSYS_1502XXXX 0 0x1000>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MDP_RSZ1>, + <&mmsys CLK_MM_MDP_DL_TXCK>, + <&mmsys CLK_MM_MDP_DL_RX>, + <&mmsys CLK_MM_IPU_DL_TXCK>, + <&mmsys CLK_MM_IPU_DL_RX>; + iommus = <&iommu M4U_PORT_MDP_RDMA0>; + mediatek,mmsys = <&mmsys>; + mediatek,mm-mutex = <&mutex>; + mediatek,mailbox-gce = <&gce>; + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>, + <&gce 22 CMDQ_THR_PRIO_LOWEST 0>, + <&gce 23 CMDQ_THR_PRIO_LOWEST 0>; + gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>, + <&gce 0x14010000 SUBSYS_1401XXXX>, + <&gce 0x14020000 SUBSYS_1402XXXX>, + <&gce 0x15020000 SUBSYS_1502XXXX>; + mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, + <CMDQ_EVENT_MDP_RDMA0_EOF>, + <CMDQ_EVENT_MDP_RSZ0_SOF>, + <CMDQ_EVENT_MDP_RSZ1_SOF>, + <CMDQ_EVENT_MDP_TDSHP_SOF>, + <CMDQ_EVENT_MDP_WROT0_SOF>, + <CMDQ_EVENT_MDP_WROT0_EOF>, + <CMDQ_EVENT_MDP_WDMA0_SOF>, + <CMDQ_EVENT_MDP_WDMA0_EOF>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>, + <CMDQ_EVENT_WPE_A_DONE>, + <CMDQ_EVENT_SPE_B_DONE>; + }; + + mdp3_rsz0: mdp3_rsz0@14003000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + mediatek,mdp3-id = <0>; + reg = <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ0>; + }; + + mdp3_rsz1: mdp3_rsz1@14004000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + mediatek,mdp3-id = <1>; + reg = <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + }; + + mdp3_wrot0: mdp3_wrot0@14005000 { + compatible = "mediatek,mt8183-mdp3-wrot"; + mediatek,mdp3-id = <0>; + reg = <0 0x14005000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + iommus = <&iommu M4U_PORT_MDP_WROT0>; + }; + + mdp3_wdma: mdp3_wdma@14006000 { + compatible = "mediatek,mt8183-mdp3-wdma"; + mediatek,mdp3-id = <0>; + reg = <0 0x14006000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WDMA0>; + iommus = <&iommu M4U_PORT_MDP_WDMA0>; + }; + ovl0: ovl@14008000 { compatible = "mediatek,mt8183-disp-ovl"; reg = <0 0x14008000 0 0x1000>; @@ -1378,6 +1480,14 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; }; + mdp3_ccorr: mdp3_ccorr@1401c000 { + compatible = "mediatek,mt8183-mdp3-ccorr"; + mediatek,mdp3-id = <0>; + reg = <0 0x1401c000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; + clocks = <&mmsys CLK_MM_MDP_CCORR>; + }; + imgsys: syscon@15020000 { compatible = "mediatek,mt8183-imgsys", "syscon"; reg = <0 0x15020000 0 0x1000>;