| Message ID | 20210820224402.2011354-1-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: zii-ultra: add PCIe PHY supply | expand |
Hi Lucas, On Fri, Aug 20, 2021 at 7:44 PM Lucas Stach <l.stach@pengutronix.de> wrote: > > The ZII Ultra board uses the same design as the EVK board supplying > PCIE_VPH with 3.3V. Add this connection to the DT to allow the PCIe > driver to enable the internal PHY regulator, as required by the > reference manual. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
On Sat, Aug 21, 2021 at 12:44:02AM +0200, Lucas Stach wrote: > The ZII Ultra board uses the same design as the EVK board supplying > PCIE_VPH with 3.3V. Add this connection to the DT to allow the PCIe > driver to enable the internal PHY regulator, as required by the > reference manual. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Applied, thanks!
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index a08a568c31d9..2222ef7b3eab 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -555,6 +555,7 @@ &pcie0 { <&clk IMX8MQ_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + vph-supply = <&vgen5_reg>; status = "okay"; }; @@ -567,6 +568,7 @@ &pcie1 { <&clk IMX8MQ_CLK_PCIE2_PHY>, <&pcie1_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + vph-supply = <&vgen5_reg>; status = "okay"; };
The ZII Ultra board uses the same design as the EVK board supplying PCIE_VPH with 3.3V. Add this connection to the DT to allow the PCIe driver to enable the internal PHY regulator, as required by the reference manual. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 2 ++ 1 file changed, 2 insertions(+)