PCI: aardvark: Fix masking and unmasking legacy INTx interrupts

Commit Message

Pali Rohár Aug. 20, 2021, 3:50 p.m. UTC

irq_mask and irq_unmask callbacks need to be properly guarded by raw spin
locks as masking/unmasking procedure needs atomic read-modify-write
operation on hardware register.

Signed-off-by: Pali Rohár <[e-mail]>
Reported-by: Marc Zyngier <[e-mail]>
Cc: [e-mail]
---
 drivers/pci/controller/pci-aardvark.c | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Marc Zyngier Aug. 20, 2021, 3:56 p.m. UTC | #1

On Fri, 20 Aug 2021 16:50:20 +0100,
Pali Rohár <[e-mail]> wrote:
> 
> irq_mask and irq_unmask callbacks need to be properly guarded by raw spin
> locks as masking/unmasking procedure needs atomic read-modify-write
> operation on hardware register.
> 
> Signed-off-by: Pali Rohár <[e-mail]>
> Reported-by: Marc Zyngier <[e-mail]>
> Cc: [e-mail]

Acked-by: Marc Zyngier <[e-mail]>

	M.

Lorenzo Pieralisi Aug. 26, 2021, 12:42 p.m. UTC | #2

On Fri, 20 Aug 2021 17:50:20 +0200, Pali Rohár wrote:
> irq_mask and irq_unmask callbacks need to be properly guarded by raw spin
> locks as masking/unmasking procedure needs atomic read-modify-write
> operation on hardware register.

Applied to pci/aardvark, thanks!

[1/1] PCI: aardvark: Fix masking and unmasking legacy INTx interrupts
      https://git.kernel.org/lpieralisi/pci/c/d212dcee27

Thanks,
Lorenzo

Patch

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index fb8060160251..a49e8bad9f4f 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -234,6 +234,7 @@  struct advk_pcie {
 	u8 wins_count;
 	struct irq_domain *irq_domain;
 	struct irq_chip irq_chip;
+	raw_spinlock_t irq_lock;
 	struct irq_domain *msi_domain;
 	struct irq_domain *msi_inner_domain;
 	struct irq_chip msi_bottom_irq_chip;
@@ -1087,22 +1088,28 @@  static void advk_pcie_irq_mask(struct irq_data *d)
 {
 	struct advk_pcie *pcie = d->domain->host_data;
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
+	unsigned long flags;
 	u32 mask;
 
+	raw_spin_lock_irqsave(&pcie->irq_lock, flags);
 	mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
 	mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
 	advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
+	raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
 }
 
 static void advk_pcie_irq_unmask(struct irq_data *d)
 {
 	struct advk_pcie *pcie = d->domain->host_data;
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
+	unsigned long flags;
 	u32 mask;
 
+	raw_spin_lock_irqsave(&pcie->irq_lock, flags);
 	mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
 	mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
 	advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
+	raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
 }
 
 static int advk_pcie_irq_map(struct irq_domain *h,
@@ -1186,6 +1193,8 @@  static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
 	struct irq_chip *irq_chip;
 	int ret = 0;
 
+	raw_spin_lock_init(&pcie->irq_lock);
+
 	pcie_intc_node =  of_get_next_child(node, NULL);
 	if (!pcie_intc_node) {
 		dev_err(dev, "No PCIe Intc node found\n");