| Message ID | 1628754078-29779-6-git-send-email-rajpat@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add QSPI and QUPv3 DT nodes for SC7280 SoC | expand |
On Thu, Aug 12, 2021 at 01:11:16PM +0530, Rajesh Patil wrote: > Configure uart5 as debug uart and split the pinctrl functions > to match with SoC dt. > > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> As I mentioned on '[4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT node', I think you need to squash the two patches to avoid breaking (temporarily) the SC7280 IDP DT due to the undefined node 'qup_uart5_default'
On 2021-08-12 21:35, Matthias Kaehlcke wrote: > On Thu, Aug 12, 2021 at 01:11:16PM +0530, Rajesh Patil wrote: >> Configure uart5 as debug uart and split the pinctrl functions >> to match with SoC dt. >> >> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> > > As I mentioned on '[4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT > node', > I think you need to squash the two patches to avoid breaking > (temporarily) > the SC7280 IDP DT due to the undefined node 'qup_uart5_default' Okay
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index c41c2d0..53993b3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -254,6 +254,7 @@ }; &uart5 { + compatible = "qcom,geni-debug-uart"; status = "okay"; }; @@ -311,18 +312,14 @@ bias-pull-up; }; -&qup_uart5_default { - tx { - pins = "gpio46"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart5_tx { + drive-strength = <2>; + bias-disable; +}; - rx { - pins = "gpio47"; - drive-strength = <2>; - bias-pull-up; - }; +&qup_uart5_rx { + drive-strength = <2>; + bias-pull-up; }; &sdc1_on {
Configure uart5 as debug uart and split the pinctrl functions to match with SoC dt. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-)