| Message ID | 20210827013415.24027-6-digetx@gmail.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | NVIDIA Tegra power management patches for 5.16 | expand |
On 27-08-21, 04:34, Dmitry Osipenko wrote: > + clk_opp_table = dev_pm_opp_set_clkname(dev, NULL); > + if (IS_ERR(clk_opp_table)) { > + dev_err(dev, "failed to set OPP clk: %pe\n", clk_opp_table); > + ret = PTR_ERR(clk_opp_table); > + goto put_hw; > + } Why do you need to do it ? OPP core already does this automatically.
27.08.2021 06:05, Viresh Kumar пишет: > On 27-08-21, 04:34, Dmitry Osipenko wrote: >> + clk_opp_table = dev_pm_opp_set_clkname(dev, NULL); >> + if (IS_ERR(clk_opp_table)) { >> + dev_err(dev, "failed to set OPP clk: %pe\n", clk_opp_table); >> + ret = PTR_ERR(clk_opp_table); >> + goto put_hw; >> + } > > Why do you need to do it ? OPP core already does this automatically. Indeed, thanks.
27.08.2021 06:28, Dmitry Osipenko пишет: > 27.08.2021 06:05, Viresh Kumar пишет: >> On 27-08-21, 04:34, Dmitry Osipenko wrote: >>> + clk_opp_table = dev_pm_opp_set_clkname(dev, NULL); >>> + if (IS_ERR(clk_opp_table)) { >>> + dev_err(dev, "failed to set OPP clk: %pe\n", clk_opp_table); >>> + ret = PTR_ERR(clk_opp_table); >>> + goto put_hw; >>> + } >> >> Why do you need to do it ? OPP core already does this automatically. > > Indeed, thanks. > Actually, it doesn't work. The devm_tegra_core_dev_init_opp_table() needs to set clk to support older device-tree and now OPP table already has clk being set. WARNING: CPU: 2 PID: 92 at drivers/opp/core.c:2146 dev_pm_opp_set_clkname+0x97/0xb8 Modules linked in: CPU: 2 PID: 92 Comm: kworker/u8:1 Tainted: G W 5.14.0-rc7-next-20210826-00181-g6389463cbb0a #9318 Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) Workqueue: events_unbound deferred_probe_work_func [<c010cc91>] (unwind_backtrace) from [<c0108d35>] (show_stack+0x11/0x14) [<c0108d35>] (show_stack) from [<c0a6c1bd>] (dump_stack_lvl+0x2b/0x34) [<c0a6c1bd>] (dump_stack_lvl) from [<c011fc47>] (__warn+0xbb/0x100) [<c011fc47>] (__warn) from [<c0a696e3>] (warn_slowpath_fmt+0x4b/0x80) [<c0a696e3>] (warn_slowpath_fmt) from [<c07407b3>] (dev_pm_opp_set_clkname+0x97/0xb8) [<c07407b3>] (dev_pm_opp_set_clkname) from [<c07407e3>] (devm_pm_opp_set_clkname+0xf/0x64) [<c07407e3>] (devm_pm_opp_set_clkname) from [<c050735b>] (devm_tegra_core_dev_init_opp_table+0x23/0x144) [<c050735b>] (devm_tegra_core_dev_init_opp_table) from [<c05aad09>] (gr3d_probe+0x111/0x348) [<c05aad09>] (gr3d_probe) from [<c05ba69b>] (platform_probe+0x43/0x84) [<c05ba69b>] (platform_probe) from [<c05b8c01>] (really_probe.part.0+0x69/0x200) [<c05b8c01>] (really_probe.part.0) from [<c05b8e0b>] (__driver_probe_device+0x73/0xd4) [<c05b8e0b>] (__driver_probe_device) from [<c05b8ea1>] (driver_probe_device+0x35/0xd0) [<c05b8ea1>] (driver_probe_device) from [<c05b92a9>] (__device_attach_driver+0x75/0x98) [<c05b92a9>] (__device_attach_driver) from [<c05b769d>] (bus_for_each_drv+0x51/0x7c) [<c05b769d>] (bus_for_each_drv) from [<c05b908f>] (__device_attach+0x8b/0x104) [<c05b908f>] (__device_attach) from [<c05b81b3>] (bus_probe_device+0x5b/0x60) [<c05b81b3>] (bus_probe_device) from [<c05b5d9f>] (device_add+0x293/0x65c) [<c05b5d9f>] (device_add) from [<c0777a4f>] (of_platform_device_create_pdata+0x63/0x88) [<c0777a4f>] (of_platform_device_create_pdata) from [<c0777b7d>] (of_platform_bus_create+0xfd/0x26c) [<c0777b7d>] (of_platform_bus_create) from [<c0777dc5>] (of_platform_populate+0x45/0x84) [<c0777dc5>] (of_platform_populate) from [<c0777e5d>] (devm_of_platform_populate+0x41/0x6c) [<c0777e5d>] (devm_of_platform_populate) from [<c05490f9>] (host1x_probe+0x1e9/0x2c8) [<c05490f9>] (host1x_probe) from [<c05ba69b>] (platform_probe+0x43/0x84) [<c05ba69b>] (platform_probe) from [<c05b8c01>] (really_probe.part.0+0x69/0x200) [<c05b8c01>] (really_probe.part.0) from [<c05b8e0b>] (__driver_probe_device+0x73/0xd4) [<c05b8e0b>] (__driver_probe_device) from [<c05b8ea1>] (driver_probe_device+0x35/0xd0) [<c05b8ea1>] (driver_probe_device) from [<c05b92a9>] (__device_attach_driver+0x75/0x98) [<c05b92a9>] (__device_attach_driver) from [<c05b769d>] (bus_for_each_drv+0x51/0x7c) [<c05b769d>] (bus_for_each_drv) from [<c05b908f>] (__device_attach+0x8b/0x104) [<c05b908f>] (__device_attach) from [<c05b81b3>] (bus_probe_device+0x5b/0x60) [<c05b81b3>] (bus_probe_device) from [<c05b8493>] (deferred_probe_work_func+0x57/0x78) [<c05b8493>] (deferred_probe_work_func) from [<c0136f73>] (process_one_work+0x147/0x3f8) [<c0136f73>] (process_one_work) from [<c0137759>] (worker_thread+0x21d/0x3f4) [<c0137759>] (worker_thread) from [<c013c10f>] (kthread+0x123/0x140) [<c013c10f>] (kthread) from [<c0100135>] (ret_from_fork+0x11/0x1c) ---[ end trace f68728a0d3053b54 ]--- tegra-gr3d 54180000.gr3d: tegra-soc: failed to set OPP clk: -16
27.08.2021 06:47, Dmitry Osipenko пишет: > 27.08.2021 06:28, Dmitry Osipenko пишет: >> 27.08.2021 06:05, Viresh Kumar пишет: >>> On 27-08-21, 04:34, Dmitry Osipenko wrote: >>>> + clk_opp_table = dev_pm_opp_set_clkname(dev, NULL); >>>> + if (IS_ERR(clk_opp_table)) { >>>> + dev_err(dev, "failed to set OPP clk: %pe\n", clk_opp_table); >>>> + ret = PTR_ERR(clk_opp_table); >>>> + goto put_hw; >>>> + } >>> >>> Why do you need to do it ? OPP core already does this automatically. >> >> Indeed, thanks. >> > > Actually, it doesn't work. > > The devm_tegra_core_dev_init_opp_table() needs to set clk to support older device-tree and now OPP table already has clk being set. > > WARNING: CPU: 2 PID: 92 at drivers/opp/core.c:2146 dev_pm_opp_set_clkname+0x97/0xb8 > Modules linked in: > CPU: 2 PID: 92 Comm: kworker/u8:1 Tainted: G W 5.14.0-rc7-next-20210826-00181-g6389463cbb0a #9318 > Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) > Workqueue: events_unbound deferred_probe_work_func > [<c010cc91>] (unwind_backtrace) from [<c0108d35>] (show_stack+0x11/0x14) > [<c0108d35>] (show_stack) from [<c0a6c1bd>] (dump_stack_lvl+0x2b/0x34) > [<c0a6c1bd>] (dump_stack_lvl) from [<c011fc47>] (__warn+0xbb/0x100) > [<c011fc47>] (__warn) from [<c0a696e3>] (warn_slowpath_fmt+0x4b/0x80) > [<c0a696e3>] (warn_slowpath_fmt) from [<c07407b3>] (dev_pm_opp_set_clkname+0x97/0xb8) > [<c07407b3>] (dev_pm_opp_set_clkname) from [<c07407e3>] (devm_pm_opp_set_clkname+0xf/0x64) > [<c07407e3>] (devm_pm_opp_set_clkname) from [<c050735b>] (devm_tegra_core_dev_init_opp_table+0x23/0x144) > [<c050735b>] (devm_tegra_core_dev_init_opp_table) from [<c05aad09>] (gr3d_probe+0x111/0x348) > [<c05aad09>] (gr3d_probe) from [<c05ba69b>] (platform_probe+0x43/0x84) > [<c05ba69b>] (platform_probe) from [<c05b8c01>] (really_probe.part.0+0x69/0x200) > [<c05b8c01>] (really_probe.part.0) from [<c05b8e0b>] (__driver_probe_device+0x73/0xd4) > [<c05b8e0b>] (__driver_probe_device) from [<c05b8ea1>] (driver_probe_device+0x35/0xd0) > [<c05b8ea1>] (driver_probe_device) from [<c05b92a9>] (__device_attach_driver+0x75/0x98) > [<c05b92a9>] (__device_attach_driver) from [<c05b769d>] (bus_for_each_drv+0x51/0x7c) > [<c05b769d>] (bus_for_each_drv) from [<c05b908f>] (__device_attach+0x8b/0x104) > [<c05b908f>] (__device_attach) from [<c05b81b3>] (bus_probe_device+0x5b/0x60) > [<c05b81b3>] (bus_probe_device) from [<c05b5d9f>] (device_add+0x293/0x65c) > [<c05b5d9f>] (device_add) from [<c0777a4f>] (of_platform_device_create_pdata+0x63/0x88) > [<c0777a4f>] (of_platform_device_create_pdata) from [<c0777b7d>] (of_platform_bus_create+0xfd/0x26c) > [<c0777b7d>] (of_platform_bus_create) from [<c0777dc5>] (of_platform_populate+0x45/0x84) > [<c0777dc5>] (of_platform_populate) from [<c0777e5d>] (devm_of_platform_populate+0x41/0x6c) > [<c0777e5d>] (devm_of_platform_populate) from [<c05490f9>] (host1x_probe+0x1e9/0x2c8) > [<c05490f9>] (host1x_probe) from [<c05ba69b>] (platform_probe+0x43/0x84) > [<c05ba69b>] (platform_probe) from [<c05b8c01>] (really_probe.part.0+0x69/0x200) > [<c05b8c01>] (really_probe.part.0) from [<c05b8e0b>] (__driver_probe_device+0x73/0xd4) > [<c05b8e0b>] (__driver_probe_device) from [<c05b8ea1>] (driver_probe_device+0x35/0xd0) > [<c05b8ea1>] (driver_probe_device) from [<c05b92a9>] (__device_attach_driver+0x75/0x98) > [<c05b92a9>] (__device_attach_driver) from [<c05b769d>] (bus_for_each_drv+0x51/0x7c) > [<c05b769d>] (bus_for_each_drv) from [<c05b908f>] (__device_attach+0x8b/0x104) > [<c05b908f>] (__device_attach) from [<c05b81b3>] (bus_probe_device+0x5b/0x60) > [<c05b81b3>] (bus_probe_device) from [<c05b8493>] (deferred_probe_work_func+0x57/0x78) > [<c05b8493>] (deferred_probe_work_func) from [<c0136f73>] (process_one_work+0x147/0x3f8) > [<c0136f73>] (process_one_work) from [<c0137759>] (worker_thread+0x21d/0x3f4) > [<c0137759>] (worker_thread) from [<c013c10f>] (kthread+0x123/0x140) > [<c013c10f>] (kthread) from [<c0100135>] (ret_from_fork+0x11/0x1c) > ---[ end trace f68728a0d3053b54 ]--- > tegra-gr3d 54180000.gr3d: tegra-soc: failed to set OPP clk: -16 > That's because devm_pm_opp_attach_genpd() holds the reference to OPP table on Tegra30 which uses multiple power domains. See gr3d_init_power() of the GR3D patch. It works in case of a single-domain hardware.
On 27-08-21, 06:47, Dmitry Osipenko wrote: > Actually, it doesn't work. > > The devm_tegra_core_dev_init_opp_table() needs to set clk to support older device-tree and now OPP table already has clk being set. > > WARNING: CPU: 2 PID: 92 at drivers/opp/core.c:2146 dev_pm_opp_set_clkname+0x97/0xb8 > Modules linked in: > CPU: 2 PID: 92 Comm: kworker/u8:1 Tainted: G W 5.14.0-rc7-next-20210826-00181-g6389463cbb0a #9318 > Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) > Workqueue: events_unbound deferred_probe_work_func > [<c010cc91>] (unwind_backtrace) from [<c0108d35>] (show_stack+0x11/0x14) > [<c0108d35>] (show_stack) from [<c0a6c1bd>] (dump_stack_lvl+0x2b/0x34) > [<c0a6c1bd>] (dump_stack_lvl) from [<c011fc47>] (__warn+0xbb/0x100) > [<c011fc47>] (__warn) from [<c0a696e3>] (warn_slowpath_fmt+0x4b/0x80) > [<c0a696e3>] (warn_slowpath_fmt) from [<c07407b3>] (dev_pm_opp_set_clkname+0x97/0xb8) > [<c07407b3>] (dev_pm_opp_set_clkname) from [<c07407e3>] (devm_pm_opp_set_clkname+0xf/0x64) > [<c07407e3>] (devm_pm_opp_set_clkname) from [<c050735b>] (devm_tegra_core_dev_init_opp_table+0x23/0x144) Why are you calling this anymore ?
27.08.2021 07:02, Viresh Kumar пишет: > On 27-08-21, 06:47, Dmitry Osipenko wrote: >> Actually, it doesn't work. >> >> The devm_tegra_core_dev_init_opp_table() needs to set clk to support older device-tree and now OPP table already has clk being set. >> >> WARNING: CPU: 2 PID: 92 at drivers/opp/core.c:2146 dev_pm_opp_set_clkname+0x97/0xb8 >> Modules linked in: >> CPU: 2 PID: 92 Comm: kworker/u8:1 Tainted: G W 5.14.0-rc7-next-20210826-00181-g6389463cbb0a #9318 >> Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) >> Workqueue: events_unbound deferred_probe_work_func >> [<c010cc91>] (unwind_backtrace) from [<c0108d35>] (show_stack+0x11/0x14) >> [<c0108d35>] (show_stack) from [<c0a6c1bd>] (dump_stack_lvl+0x2b/0x34) >> [<c0a6c1bd>] (dump_stack_lvl) from [<c011fc47>] (__warn+0xbb/0x100) >> [<c011fc47>] (__warn) from [<c0a696e3>] (warn_slowpath_fmt+0x4b/0x80) >> [<c0a696e3>] (warn_slowpath_fmt) from [<c07407b3>] (dev_pm_opp_set_clkname+0x97/0xb8) >> [<c07407b3>] (dev_pm_opp_set_clkname) from [<c07407e3>] (devm_pm_opp_set_clkname+0xf/0x64) >> [<c07407e3>] (devm_pm_opp_set_clkname) from [<c050735b>] (devm_tegra_core_dev_init_opp_table+0x23/0x144) > > Why are you calling this anymore ? Older device-trees don't have OPPs, meanwhile drivers will use dev_pm_opp_set_rate() and it requires OPP table to be set up using devm_pm_opp_set_clkname(). The devm_tegra_core_dev_init_opp_table() is a common helper that sets up OPP table for Tegra drivers and it sets the clk.
On 27-08-21, 07:08, Dmitry Osipenko wrote: > 27.08.2021 07:02, Viresh Kumar пишет: > > On 27-08-21, 06:47, Dmitry Osipenko wrote: > >> Actually, it doesn't work. > >> > >> The devm_tegra_core_dev_init_opp_table() needs to set clk to support older device-tree and now OPP table already has clk being set. > >> > >> WARNING: CPU: 2 PID: 92 at drivers/opp/core.c:2146 dev_pm_opp_set_clkname+0x97/0xb8 > >> Modules linked in: > >> CPU: 2 PID: 92 Comm: kworker/u8:1 Tainted: G W 5.14.0-rc7-next-20210826-00181-g6389463cbb0a #9318 > >> Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) > >> Workqueue: events_unbound deferred_probe_work_func > >> [<c010cc91>] (unwind_backtrace) from [<c0108d35>] (show_stack+0x11/0x14) > >> [<c0108d35>] (show_stack) from [<c0a6c1bd>] (dump_stack_lvl+0x2b/0x34) > >> [<c0a6c1bd>] (dump_stack_lvl) from [<c011fc47>] (__warn+0xbb/0x100) > >> [<c011fc47>] (__warn) from [<c0a696e3>] (warn_slowpath_fmt+0x4b/0x80) > >> [<c0a696e3>] (warn_slowpath_fmt) from [<c07407b3>] (dev_pm_opp_set_clkname+0x97/0xb8) > >> [<c07407b3>] (dev_pm_opp_set_clkname) from [<c07407e3>] (devm_pm_opp_set_clkname+0xf/0x64) > >> [<c07407e3>] (devm_pm_opp_set_clkname) from [<c050735b>] (devm_tegra_core_dev_init_opp_table+0x23/0x144) > > > > Why are you calling this anymore ? > > Older device-trees don't have OPPs, meanwhile drivers will use > dev_pm_opp_set_rate() and it requires OPP table to be set up using > devm_pm_opp_set_clkname(). > > The devm_tegra_core_dev_init_opp_table() is a common helper that sets up > OPP table for Tegra drivers and it sets the clk. Ahh, I see. that's okay then. Just add a comment over it to specify the same. Doing devm_pm_opp_set_clkname(dev, NULL) is special and looks suspicious otherwise.
27.08.2021 07:13, Viresh Kumar пишет: > On 27-08-21, 07:08, Dmitry Osipenko wrote: >> 27.08.2021 07:02, Viresh Kumar пишет: >>> On 27-08-21, 06:47, Dmitry Osipenko wrote: >>>> Actually, it doesn't work. >>>> >>>> The devm_tegra_core_dev_init_opp_table() needs to set clk to support older device-tree and now OPP table already has clk being set. >>>> >>>> WARNING: CPU: 2 PID: 92 at drivers/opp/core.c:2146 dev_pm_opp_set_clkname+0x97/0xb8 >>>> Modules linked in: >>>> CPU: 2 PID: 92 Comm: kworker/u8:1 Tainted: G W 5.14.0-rc7-next-20210826-00181-g6389463cbb0a #9318 >>>> Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) >>>> Workqueue: events_unbound deferred_probe_work_func >>>> [<c010cc91>] (unwind_backtrace) from [<c0108d35>] (show_stack+0x11/0x14) >>>> [<c0108d35>] (show_stack) from [<c0a6c1bd>] (dump_stack_lvl+0x2b/0x34) >>>> [<c0a6c1bd>] (dump_stack_lvl) from [<c011fc47>] (__warn+0xbb/0x100) >>>> [<c011fc47>] (__warn) from [<c0a696e3>] (warn_slowpath_fmt+0x4b/0x80) >>>> [<c0a696e3>] (warn_slowpath_fmt) from [<c07407b3>] (dev_pm_opp_set_clkname+0x97/0xb8) >>>> [<c07407b3>] (dev_pm_opp_set_clkname) from [<c07407e3>] (devm_pm_opp_set_clkname+0xf/0x64) >>>> [<c07407e3>] (devm_pm_opp_set_clkname) from [<c050735b>] (devm_tegra_core_dev_init_opp_table+0x23/0x144) >>> >>> Why are you calling this anymore ? >> >> Older device-trees don't have OPPs, meanwhile drivers will use >> dev_pm_opp_set_rate() and it requires OPP table to be set up using >> devm_pm_opp_set_clkname(). >> >> The devm_tegra_core_dev_init_opp_table() is a common helper that sets up >> OPP table for Tegra drivers and it sets the clk. > > Ahh, I see. that's okay then. Just add a comment over it to specify the same. > Doing devm_pm_opp_set_clkname(dev, NULL) is special and looks suspicious > otherwise. I'll add comment, thanks.
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 50091c4ec948..ea552f7ed922 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -505,6 +505,90 @@ static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, writel(value, pmc->scratch + offset); } +static const char * const tegra_pd_no_perf_compats[] = { + "nvidia,tegra20-sclk", + "nvidia,tegra30-sclk", + "nvidia,tegra30-pllc", + "nvidia,tegra30-plle", + "nvidia,tegra30-pllm", + "nvidia,tegra20-dc", + "nvidia,tegra30-dc", + "nvidia,tegra20-emc", + "nvidia,tegra30-emc", + NULL, +}; + +static int tegra_pmc_pd_get_performance_state(struct generic_pm_domain *genpd, + struct device *dev, + bool *dev_suspended) +{ + struct opp_table *hw_opp_table, *clk_opp_table; + struct dev_pm_opp *opp; + u32 hw_version; + int ret; + + /* + * The EMC devices are a special case because we have a protection + * from non-EMC drivers getting clock handle before EMC driver is + * fully initialized. The goal of the protection is to prevent + * devfreq driver from getting failures if it will try to change + * EMC clock rate until clock is fully initialized. The EMC drivers + * will initialize the performance state by themselves. + * + * Display controller also is a special case because only controller + * driver could get the clock rate based on configuration of internal + * divider. + * + * Clock driver uses its own state syncing. + */ + if (of_device_compatible_match(dev->of_node, tegra_pd_no_perf_compats)) + return 0; + + if (of_machine_is_compatible("nvidia,tegra20")) + hw_version = BIT(tegra_sku_info.soc_process_id); + else + hw_version = BIT(tegra_sku_info.soc_speedo_id); + + hw_opp_table = dev_pm_opp_set_supported_hw(dev, &hw_version, 1); + if (IS_ERR(hw_opp_table)) { + dev_err(dev, "failed to set OPP supported HW: %pe\n", + hw_opp_table); + return PTR_ERR(hw_opp_table); + } + + clk_opp_table = dev_pm_opp_set_clkname(dev, NULL); + if (IS_ERR(clk_opp_table)) { + dev_err(dev, "failed to set OPP clk: %pe\n", clk_opp_table); + ret = PTR_ERR(clk_opp_table); + goto put_hw; + } + + ret = devm_pm_opp_of_add_table(dev); + if (ret) { + dev_err(dev, "failed to add OPP table: %d\n", ret); + goto put_clk; + } + + opp = dev_pm_opp_from_clk_rate(dev); + if (IS_ERR(opp)) { + dev_err(dev, "failed to get current OPP: %pe\n", opp); + ret = PTR_ERR(opp); + } else { + ret = dev_pm_opp_get_required_pstate(opp, 0); + dev_pm_opp_put(opp); + } + + *dev_suspended = true; + + dev_pm_opp_of_remove_table(dev); +put_clk: + dev_pm_opp_put_clkname(clk_opp_table); +put_hw: + dev_pm_opp_put_supported_hw(hw_opp_table); + + return ret; +} + /* * TODO Figure out a way to call this with the struct tegra_pmc * passed in. * This currently doesn't work because readx_poll_timeout() can only operate @@ -1237,6 +1321,7 @@ static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) pg->id = id; pg->genpd.name = np->name; + pg->genpd.get_performance_state = tegra_pmc_pd_get_performance_state; pg->genpd.power_off = tegra_genpd_power_off; pg->genpd.power_on = tegra_genpd_power_on; pg->pmc = pmc; @@ -1353,6 +1438,7 @@ static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) return -ENOMEM; genpd->name = np->name; + genpd->get_performance_state = tegra_pmc_pd_get_performance_state; genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state;
Implement get_performance_state() callback of power domains to initialize theirs performance state in accordance to the clock rate of attached device. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/soc/tegra/pmc.c | 86 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+)