| Message ID | 20210830172140.414-5-caihuoqing@baidu.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add driver support for NXP IMX8QXP ADC | expand |
On Tue, 31 Aug 2021 01:21:38 +0800, Cai Huoqing wrote: > The NXP i.MX 8QuadXPlus SOC has a new ADC IP, so add the binding > documentation for NXP IMX8QXP ADC > > Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> > --- > .../bindings/iio/adc/nxp,imx8qxp-adc.yaml | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: make[1]: *** Deleting file 'Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.example.dts' Traceback (most recent call last): File "/usr/local/bin/dt-extract-example", line 45, in <module> binding = yaml.load(open(args.yamlfile, encoding='utf-8').read()) File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 434, in load return constructor.get_single_data() File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 120, in get_single_data node = self.composer.get_single_node() File "_ruamel_yaml.pyx", line 706, in _ruamel_yaml.CParser.get_single_node File "_ruamel_yaml.pyx", line 724, in _ruamel_yaml.CParser._compose_document File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node File "_ruamel_yaml.pyx", line 773, in _ruamel_yaml.CParser._compose_node File "_ruamel_yaml.pyx", line 848, in _ruamel_yaml.CParser._compose_sequence_node File "_ruamel_yaml.pyx", line 904, in _ruamel_yaml.CParser._parse_next_event ruamel.yaml.scanner.ScannerError: while scanning a block scalar in "<unicode string>", line 65, column 5 found a tab character where an indentation space is expected in "<unicode string>", line 71, column 1 make[1]: *** [Documentation/devicetree/bindings/Makefile:20: Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.example.dts] Error 1 make[1]: *** Waiting for unfinished jobs.... ./Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml: while scanning a block scalar in "<unicode string>", line 65, column 5 found a tab character where an indentation space is expected in "<unicode string>", line 71, column 1 /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml: ignoring, error parsing file warning: no schema found in file: ./Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml make: *** [Makefile:1419: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1522287 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Tue, 31 Aug 2021 01:21:38 +0800 Cai Huoqing <caihuoqing@baidu.com> wrote: > The NXP i.MX 8QuadXPlus SOC has a new ADC IP, so add the binding > documentation for NXP IMX8QXP ADC > > Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> > --- > .../bindings/iio/adc/nxp,imx8qxp-adc.yaml | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml > > diff --git a/Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml b/Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml > new file mode 100644 > index 000000000000..542329e6a785 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml > @@ -0,0 +1,85 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP IMX8QXP ADC bindings > + > +maintainers: > + - Cai Huoqing <caihuoqing@baidu.com> > + > +description: > + Supports the ADC found on the IMX8QXP SoC. > + > +properties: > + compatible: > + const: nxp,imx8qxp-adc > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 2 > + > + clock-names: > + items: > + - const: per > + - const: ipg > + > + assigned-clocks: > + maxItems: 1 > + > + assigned-clocks-rate: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + status: > + const: disable > + > + "#io-channel-cells": > + const: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupts-parent > + - clocks > + - clock-names > + - assigned-clocks > + - assigned-clock-rates > + - power-domains > + - state > + - "#address-cells" > + - "#size-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/firmware/imx/rsrc.h> > + soc { > + #address-cells = <1>; > + #size-cells = <1>; > + adc@5a880000 { Clearly some indentation issues here. > + compatible = "nxp,imx8qxp-adc"; > + reg = <0x0 0x5a880000 0x0 0x10000>; > + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX_SC_R_ADC_0>, > + <&clk IMX_ADMA_LPCG_ADC_0_IPG_CLK>; > + clock-names = "per", "ipg"; > + assigned-clocks = <&clk IMX_SC_R_ADC_0>; > + assigned-clock-rates = <24000000>; > + power-domains = <&pm, IMX_SC_R_ADC_0>; > + status = "disabled"; Don't mark the example disabled. > + #io-channel-cells = <1> > + }; > + }; > +...
diff --git a/Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml b/Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml new file mode 100644 index 000000000000..542329e6a785 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP IMX8QXP ADC bindings + +maintainers: + - Cai Huoqing <caihuoqing@baidu.com> + +description: + Supports the ADC found on the IMX8QXP SoC. + +properties: + compatible: + const: nxp,imx8qxp-adc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: per + - const: ipg + + assigned-clocks: + maxItems: 1 + + assigned-clocks-rate: + maxItems: 1 + + power-domains: + maxItems: 1 + + status: + const: disable + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - interrupts-parent + - clocks + - clock-names + - assigned-clocks + - assigned-clock-rates + - power-domains + - state + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/firmware/imx/rsrc.h> + soc { + #address-cells = <1>; + #size-cells = <1>; + adc@5a880000 { + compatible = "nxp,imx8qxp-adc"; + reg = <0x0 0x5a880000 0x0 0x10000>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX_SC_R_ADC_0>, + <&clk IMX_ADMA_LPCG_ADC_0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_ADC_0>; + assigned-clock-rates = <24000000>; + power-domains = <&pm, IMX_SC_R_ADC_0>; + status = "disabled"; + #io-channel-cells = <1> + }; + }; +...
The NXP i.MX 8QuadXPlus SOC has a new ADC IP, so add the binding documentation for NXP IMX8QXP ADC Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> --- .../bindings/iio/adc/nxp,imx8qxp-adc.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml