| Message ID | 20210809134547.689560-14-clg@kaod.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ppc/pnv: Extend the powernv10 machine | expand |
On Mon, Aug 09, 2021 at 03:45:34PM +0200, Cédric Le Goater wrote: > Still needs some refinements on the XSCOM registers. > > Signed-off-by: Cédric Le Goater <clg@kaod.org> > --- > include/hw/ppc/pnv.h | 3 +++ > hw/ppc/pnv.c | 34 ++++++++++++++++++++++++++++++++++ > 2 files changed, 37 insertions(+) > > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index a299fbc7f25c..13495423283a 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -128,6 +128,9 @@ struct Pnv10Chip { > Pnv9Psi psi; > PnvLpcController lpc; > PnvOCC occ; > + > + uint32_t nr_quads; > + PnvQuad *quads; > }; > > #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index f75d90e61fa8..f670d97c5f91 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -1605,6 +1605,34 @@ static void pnv_chip_power10_instance_init(Object *obj) > object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); > } > > + > +static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) > +{ > + PnvChip *chip = PNV_CHIP(chip10); > + int i; > + > + chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); > + chip10->quads = g_new0(PnvQuad, chip10->nr_quads); > + > + for (i = 0; i < chip10->nr_quads; i++) { > + char eq_name[32]; > + PnvQuad *eq = &chip10->quads[i]; > + PnvCore *pnv_core = chip->cores[i * 4]; > + int core_id = CPU_CORE(pnv_core)->core_id; > + > + snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); > + object_initialize_child_with_props(OBJECT(chip), eq_name, eq, > + sizeof(*eq), TYPE_PNV_QUAD, > + &error_fatal, NULL); > + > + object_property_set_int(OBJECT(eq), "id", core_id, &error_fatal); "id" might not be a good name for this, since "id" on QOM objects is nearly always the (usually) user assigned name - which is a string. > + qdev_realize(DEVICE(eq), NULL, &error_fatal); > + > + pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->id), > + &eq->xscom_regs); > + } > +} > + > static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) > { > PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); > @@ -1626,6 +1654,12 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) > return; > } > > + pnv_chip_power10_quad_realize(chip10, &local_err); > + if (local_err) { > + error_propagate(errp, local_err); > + return; > + } > + > /* XIVE2 interrupt controller (POWER10) */ > object_property_set_int(OBJECT(&chip10->xive), "ic-bar", > PNV10_XIVE2_IC_BASE(chip), &error_fatal);
On 8/25/21 8:09 AM, David Gibson wrote: > On Mon, Aug 09, 2021 at 03:45:34PM +0200, Cédric Le Goater wrote: >> Still needs some refinements on the XSCOM registers. >> >> Signed-off-by: Cédric Le Goater <clg@kaod.org> >> --- >> include/hw/ppc/pnv.h | 3 +++ >> hw/ppc/pnv.c | 34 ++++++++++++++++++++++++++++++++++ >> 2 files changed, 37 insertions(+) >> >> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h >> index a299fbc7f25c..13495423283a 100644 >> --- a/include/hw/ppc/pnv.h >> +++ b/include/hw/ppc/pnv.h >> @@ -128,6 +128,9 @@ struct Pnv10Chip { >> Pnv9Psi psi; >> PnvLpcController lpc; >> PnvOCC occ; >> + >> + uint32_t nr_quads; >> + PnvQuad *quads; >> }; >> >> #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) >> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c >> index f75d90e61fa8..f670d97c5f91 100644 >> --- a/hw/ppc/pnv.c >> +++ b/hw/ppc/pnv.c >> @@ -1605,6 +1605,34 @@ static void pnv_chip_power10_instance_init(Object *obj) >> object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); >> } >> >> + >> +static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) >> +{ >> + PnvChip *chip = PNV_CHIP(chip10); >> + int i; >> + >> + chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); >> + chip10->quads = g_new0(PnvQuad, chip10->nr_quads); >> + >> + for (i = 0; i < chip10->nr_quads; i++) { >> + char eq_name[32]; >> + PnvQuad *eq = &chip10->quads[i]; >> + PnvCore *pnv_core = chip->cores[i * 4]; >> + int core_id = CPU_CORE(pnv_core)->core_id; >> + >> + snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); >> + object_initialize_child_with_props(OBJECT(chip), eq_name, eq, >> + sizeof(*eq), TYPE_PNV_QUAD, >> + &error_fatal, NULL); >> + >> + object_property_set_int(OBJECT(eq), "id", core_id, &error_fatal); > > "id" might not be a good name for this, since "id" on QOM objects is > nearly always the (usually) user assigned name - which is a string. I will change PnvQuad before resending. Thanks, C. > >> + qdev_realize(DEVICE(eq), NULL, &error_fatal); >> + >> + pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->id), >> + &eq->xscom_regs); >> + } >> +} >> + >> static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) >> { >> PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); >> @@ -1626,6 +1654,12 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) >> return; >> } >> >> + pnv_chip_power10_quad_realize(chip10, &local_err); >> + if (local_err) { >> + error_propagate(errp, local_err); >> + return; >> + } >> + >> /* XIVE2 interrupt controller (POWER10) */ >> object_property_set_int(OBJECT(&chip10->xive), "ic-bar", >> PNV10_XIVE2_IC_BASE(chip), &error_fatal); >
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index a299fbc7f25c..13495423283a 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -128,6 +128,9 @@ struct Pnv10Chip { Pnv9Psi psi; PnvLpcController lpc; PnvOCC occ; + + uint32_t nr_quads; + PnvQuad *quads; }; #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index f75d90e61fa8..f670d97c5f91 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1605,6 +1605,34 @@ static void pnv_chip_power10_instance_init(Object *obj) object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); } + +static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) +{ + PnvChip *chip = PNV_CHIP(chip10); + int i; + + chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); + chip10->quads = g_new0(PnvQuad, chip10->nr_quads); + + for (i = 0; i < chip10->nr_quads; i++) { + char eq_name[32]; + PnvQuad *eq = &chip10->quads[i]; + PnvCore *pnv_core = chip->cores[i * 4]; + int core_id = CPU_CORE(pnv_core)->core_id; + + snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); + object_initialize_child_with_props(OBJECT(chip), eq_name, eq, + sizeof(*eq), TYPE_PNV_QUAD, + &error_fatal, NULL); + + object_property_set_int(OBJECT(eq), "id", core_id, &error_fatal); + qdev_realize(DEVICE(eq), NULL, &error_fatal); + + pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->id), + &eq->xscom_regs); + } +} + static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) { PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); @@ -1626,6 +1654,12 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) return; } + pnv_chip_power10_quad_realize(chip10, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + /* XIVE2 interrupt controller (POWER10) */ object_property_set_int(OBJECT(&chip10->xive), "ic-bar", PNV10_XIVE2_IC_BASE(chip), &error_fatal);
Still needs some refinements on the XSCOM registers. Signed-off-by: Cédric Le Goater <clg@kaod.org> --- include/hw/ppc/pnv.h | 3 +++ hw/ppc/pnv.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+)