diff mbox series

[V6,4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT node

Message ID 1629983731-10595-5-git-send-email-rajpat@codeaurora.org (mailing list archive)
State Superseded
Headers show
Series Add QSPI and QUPv3 DT nodes for SC7280 SoC | expand

Commit Message

Rajesh Patil Aug. 26, 2021, 1:15 p.m. UTC 
From: Roja Rani Yarubandi <rojay@codeaurora.org>

Update the compatible string as "qcom,geni-uart".
Add interconnects and power-domains. Split the pinctrl
functions and correct the gpio pins.

split the pinctrl functions to match with SoC dt

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 ++++++++-----------
 arch/arm64/boot/dts/qcom/sc7280.dtsi     | 30 +++++++++++++++++++++++++-----
 2 files changed, 33 insertions(+), 16 deletions(-)

Comments

Matthias Kaehlcke Aug. 26, 2021, 9:01 p.m. UTC | #1 
On Thu, Aug 26, 2021 at 06:45:28PM +0530, Rajesh Patil wrote:
> From: Roja Rani Yarubandi <rojay@codeaurora.org>
> 
> Update the compatible string as "qcom,geni-uart".
> Add interconnects and power-domains. Split the pinctrl
> functions and correct the gpio pins.

You could say that uart5 was formerly treated as special
(dedicated debug uart) and that the change removes this
specialness and makes it look like any other UART.

> split the pinctrl functions to match with SoC dt

The message should say that this is about the 7280-idp

> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>

The change itself looks good to me, the above are only nits to improve
the commit message, so:

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Rajesh Patil Aug. 31, 2021, 3:27 p.m. UTC | #2 
On 2021-08-27 02:31, Matthias Kaehlcke wrote:
> On Thu, Aug 26, 2021 at 06:45:28PM +0530, Rajesh Patil wrote:
>> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>> 
>> Update the compatible string as "qcom,geni-uart".
>> Add interconnects and power-domains. Split the pinctrl
>> functions and correct the gpio pins.
> 
> You could say that uart5 was formerly treated as special
> (dedicated debug uart) and that the change removes this
> specialness and makes it look like any other UART.
> 

Okay

>> split the pinctrl functions to match with SoC dt
> 
> The message should say that this is about the 7280-idp
> 
>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> 
> The change itself looks good to me, the above are only nits to improve
> the commit message, so:
> 
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index c41c2d0..53993b3 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -254,6 +254,7 @@ 
 };
 
 &uart5 {
+	compatible = "qcom,geni-debug-uart";
 	status = "okay";
 };
 
@@ -311,18 +312,14 @@ 
 	bias-pull-up;
 };
 
-&qup_uart5_default {
-	tx {
-		pins = "gpio46";
-		drive-strength = <2>;
-		bias-disable;
-	};
+&qup_uart5_tx {
+	drive-strength = <2>;
+	bias-disable;
+};
 
-	rx {
-		pins = "gpio47";
-		drive-strength = <2>;
-		bias-pull-up;
-	};
+&qup_uart5_rx {
+	drive-strength = <2>;
+	bias-pull-up;
 };
 
 &sdc1_on {
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index da3cf19..a3c11b0 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -861,13 +861,18 @@ 
 			};
 
 			uart5: serial@994000 {
-				compatible = "qcom,geni-debug-uart";
+				compatible = "qcom,geni-uart";
 				reg = <0 0x00994000 0 0x4000>;
 				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 				clock-names = "se";
 				pinctrl-names = "default";
-				pinctrl-0 = <&qup_uart5_default>;
+				pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
 				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 
@@ -2255,9 +2260,24 @@ 
 				function = "qup04";
 			};
 
-			qup_uart5_default: qup-uart5-default {
-				pins = "gpio46", "gpio47";
-				function = "qup13";
+			qup_uart5_cts: qup-uart5-cts {
+				pins = "gpio20";
+				function = "qup05";
+			};
+
+			qup_uart5_rts: qup-uart5-rts {
+				pins = "gpio21";
+				function = "qup05";
+			};
+
+			qup_uart5_tx: qup-uart5-tx {
+				pins = "gpio22";
+				function = "qup05";
+			};
+
+			qup_uart5_rx: qup-uart5-rx {
+				pins = "gpio23";
+				function = "qup05";
 			};
 
 			qup_uart6_cts: qup-uart6-cts {