| Message ID | 20210902161543.417092-25-f4bug@amsat.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | accel: Move has_work() from SysemuCPUOps to AccelOpsClass | expand |
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote: > Restrict has_work() to TCG sysemu. > > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > target/rx/cpu.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/target/rx/cpu.c b/target/rx/cpu.c > index 25a4aa2976d..0d0cf6f9028 100644 > --- a/target/rx/cpu.c > +++ b/target/rx/cpu.c > @@ -41,11 +41,13 @@ static void rx_cpu_synchronize_from_tb(CPUState *cs, > cpu->env.pc = tb->pc; > } > > +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) > static bool rx_cpu_has_work(CPUState *cs) No CONFIG_TCG, otherwise, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 25a4aa2976d..0d0cf6f9028 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -41,11 +41,13 @@ static void rx_cpu_synchronize_from_tb(CPUState *cs, cpu->env.pc = tb->pc; } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool rx_cpu_has_work(CPUState *cs) { return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ static void rx_cpu_reset(DeviceState *dev) { @@ -189,6 +191,7 @@ static const struct TCGCPUOps rx_tcg_ops = { .tlb_fill = rx_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = rx_cpu_has_work, .cpu_exec_interrupt = rx_cpu_exec_interrupt, .do_interrupt = rx_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ @@ -206,7 +209,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data) &rcc->parent_reset); cc->class_by_name = rx_cpu_class_by_name; - cc->has_work = rx_cpu_has_work; cc->dump_state = rx_cpu_dump_state; cc->set_pc = rx_cpu_set_pc;
Restrict has_work() to TCG sysemu. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- target/rx/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)