@@ -41,6 +41,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb
new file mode 100644
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Homestar board device tree source
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+/dts-v1/;
+
+#include "sc7180-trogdor-homestar.dtsi"
+
+/ {
+ model = "Google Homestar (rev2)";
+ compatible = "google,homestar-rev2","google,homestar-rev23", "qcom,sc7180";
+};
+
+&panel {
+ /delete-property/hpd-gpios;
+ no-hpd;
+};
new file mode 100644
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Homestar board device tree source
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+/dts-v1/;
+
+#include "sc7180-trogdor-homestar.dtsi"
+
+/ {
+ model = "Google Homestar (rev3+)";
+ compatible = "google,homestar", "qcom,sc7180";
+};
new file mode 100644
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Homestar board device tree source
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+#include "sc7180.dtsi"
+
+ap_ec_spi: &spi6 {};
+ap_h1_spi: &spi0 {};
+
+#include "sc7180-trogdor.dtsi"
+
+/ {
+ /* BOARD-SPECIFIC TOP LEVEL NODES */
+
+ max98360a_1: max98360a_1 {
+ compatible = "maxim,max98360a";
+ #sound-dai-cells = <0>;
+ };
+
+ max98360a_2: max98360a_2 {
+ compatible = "maxim,max98360a";
+ #sound-dai-cells = <0>;
+ };
+
+ max98360a_3: max98360a_3 {
+ compatible = "maxim,max98360a";
+ #sound-dai-cells = <0>;
+ };
+
+ pp3300_touch: pp3300-touch {
+ compatible = "regulator-fixed";
+ regulator-name = "pp3300_touch";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&en_pp3300_touch>;
+
+ vin-supply = <&pp3300_a>;
+ };
+
+ thermal-zones {
+ skin_temp_thermal: skin-temp-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm6150_adc_tm 1>;
+ sustainable-power = <814>;
+
+ trips {
+ skin_temp_alert0: trip-point0 {
+ temperature = <55000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ skin_temp_alert1: trip-point1 {
+ temperature = <58000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ skin-temp-crit {
+ temperature = <73000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&skin_temp_alert0>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&skin_temp_alert1>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+};
+
+&ap_tp_i2c {
+ status = "disabled";
+};
+
+ap_ts_pen_1v8: &i2c4 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ ap_ts: touchscreen@14 {
+ compatible = "goodix,gt7375p";
+ reg = <0x14>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_l>, <&ts_reset_l>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
+
+ vdd-supply = <&pp3300_touch>;
+ };
+};
+
+/* Panel controls backlight over aux channel */
+
+&backlight {
+ status = "disabled";
+};
+
+&camcc {
+ status = "okay";
+};
+
+&panel {
+ compatible = "samsung,atna33xc20";
+ enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
+ /delete-property/ backlight;
+};
+
+&pm6150_adc {
+ skin-temp-thermistor@4d {
+ reg = <ADC5_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm6150_adc_tm {
+ status = "okay";
+
+ skin-temp-thermistor@1 {
+ reg = <1>;
+ io-channels = <&pm6150_adc ADC5_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
+&pp3300_dx_edp {
+ gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
+};
+
+&secondary_mi2s {
+ qcom,playback-sd-lines = <0 1>;
+};
+
+&sound_multimedia1_codec {
+ sound-dai = <&max98360a>, <&max98360a_1>, <&max98360a_2>, <&max98360a_3> ;
+};
+
+&wifi {
+ qcom,ath10k-calibration-variant = "GO_HOMESTAR";
+};
+
+/* PINCTRL - modifications to sc7180-trogdor.dtsi */
+
+&en_pp3300_dx_edp {
+ pinmux {
+ pins = "gpio67";
+ };
+
+ pinconf {
+ pins = "gpio67";
+ };
+};
+
+&sec_mi2s_active{
+ pinmux {
+ pins = "gpio49", "gpio50", "gpio51", "gpio52";
+ function = "mi2s_1";
+ };
+};
+
+&ts_reset_l {
+ pinconf {
+ /*
+ * We want reset state by default and it will be up to the
+ * driver to disable this when it's ready.
+ */
+ output-low;
+ };
+};
+
+/* PINCTRL - board-specific pinctrl */
+
+&tlmm {
+ gpio-line-names = "HUB_RST_L",
+ "AP_RAM_ID0",
+ "AP_SKU_ID2",
+ "AP_RAM_ID1",
+ "",
+ "AP_RAM_ID2",
+ "UF_CAM_EN",
+ "WF_CAM_EN",
+ "TS_RESET_L",
+ "TS_INT_L",
+ "",
+ "EDP_BRIJ_IRQ",
+ "AP_EDP_BKLTEN",
+ "UF_CAM_MCLK",
+ "WF_CAM_CLK",
+ "EDP_BRIJ_I2C_SDA",
+ "EDP_BRIJ_I2C_SCL",
+ "UF_CAM_SDA",
+ "UF_CAM_SCL",
+ "WF_CAM_SDA",
+ "WF_CAM_SCL",
+ "AVEE_LCD_EN",
+ "",
+ "AMP_EN",
+ "AMP_EN2",
+ "AP_SAR_SENSOR_SDA",
+ "AP_SAR_SENSOR_SCL",
+ "SEL_LCM",
+ "HP_IRQ",
+ "WF_CAM_RST_L",
+ "UF_CAM_RST_L",
+ "AP_BRD_ID2",
+ "BRIJ_SUSPEND",
+ "AP_BRD_ID0",
+ "AP_H1_SPI_MISO",
+ "AP_H1_SPI_MOSI",
+ "AP_H1_SPI_CLK",
+ "AP_H1_SPI_CS_L",
+ "BT_UART_CTS",
+ "BT_UART_RTS",
+ "BT_UART_TXD",
+ "BT_UART_RXD",
+ "H1_AP_INT_ODL",
+ "",
+ "UART_AP_TX_DBG_RX",
+ "UART_DBG_TX_AP_RX",
+ "HP_I2C_SDA",
+ "HP_I2C_SCL",
+ "FORCED_USB_BOOT",
+ "AMP_BCLK",
+ "AMP_LRCLK",
+ "AMP_DIN",
+ "AMP_DIN_2",
+ "HP_BCLK",
+ "HP_LRCLK",
+ "HP_DOUT",
+ "HP_DIN",
+ "HP_MCLK",
+ "AP_SKU_ID0",
+ "AP_EC_SPI_MISO",
+ "AP_EC_SPI_MOSI",
+ "AP_EC_SPI_CLK",
+ "AP_EC_SPI_CS_L",
+ "AP_SPI_CLK",
+ "AP_SPI_MOSI",
+ "AP_SPI_MISO",
+ /*
+ * AP_FLASH_WP_L is crossystem ABI. Schematics
+ * call it BIOS_FLASH_WP_L.
+ */
+ "AP_FLASH_WP_L",
+ "EN_PP3300_DX_EDP",
+ "AP_SPI_CS0_L",
+ "SD_CD_ODL",
+ "",
+ "",
+ "",
+ "WLAN_SW_CTRL",
+ "",
+ "REPORT_E",
+ "VDD_RESET_1.8V",
+ "ID0",
+ "",
+ "ID1",
+ "AVDD_LCD_EN",
+ "MIPI_1.8V_EN",
+ "",
+ "CODEC_PWR_EN",
+ "HUB_EN",
+ "",
+ "PP1800_MIPI_SW_EN",
+ "EN_PP3300_TOUCH",
+ "",
+ "",
+ "AP_SKU_ID1",
+ "AP_RST_REQ",
+ "",
+ "AP_BRD_ID1",
+ "AP_EC_INT_L",
+ "SDM_GRFC_3",
+ "",
+ "",
+ "BOOT_CONFIG_4",
+ "BOOT_CONFIG_2",
+ "",
+ "",
+ "",
+ "",
+ "EDP_BRIJ_EN",
+ "",
+ "",
+ "BOOT_CONFIG_3",
+ "WCI2_LTE_COEX_TXD",
+ "WCI2_LTE_COEX_RXD",
+ "",
+ "",
+ "",
+ "",
+ "FORCED_USB_BOOT_POL",
+ "AP_TS_PEN_I2C_SDA",
+ "AP_TS_PEN_I2C_SCL",
+ "DP_HOT_PLUG_DET",
+ "EC_IN_RW_ODL";
+
+ en_pp3300_touch: en-pp3300-touch {
+ pinmux {
+ pins = "gpio87";
+ function = "gpio";
+ };
+
+ pinconf {
+ pins = "gpio87";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+};
Homestar is a trogdor variant. The DT bits are essentially the same as in the downstream tree, except for: - skip -rev0 and rev1 which were early builds and have their issues, it's not very useful to support them upstream - don't include the .dtsi for the MIPI cameras, which doesn't exist upstream Signed-off-by: Matthias Kaehlcke <mka@chromium.org> --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../dts/qcom/sc7180-trogdor-homestar-r2.dts | 20 ++ .../dts/qcom/sc7180-trogdor-homestar-r3.dts | 15 + .../dts/qcom/sc7180-trogdor-homestar.dtsi | 335 ++++++++++++++++++ 4 files changed, 372 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi