| Message ID | 20210913060231.15619-2-chiawei_wang@aspeedtech.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm: aspeed: Add UART routing support | expand |
> From: Rob Herring <robh@kernel.org> > Sent: Monday, September 13, 2021 8:19 PM > > On Mon, 13 Sep 2021 14:02:28 +0800, Chia-Wei Wang wrote: > > Convert the bindings of Aspeed LPC from text file into YAML schema. > > > > Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> > > --- > > .../devicetree/bindings/mfd/aspeed-lpc.txt | 157 --------------- > > .../devicetree/bindings/mfd/aspeed-lpc.yaml | 187 > ++++++++++++++++++ > > 2 files changed, 187 insertions(+), 157 deletions(-) delete mode > > 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > > create mode 100644 > > Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m > dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Documentation/devicetree/bindings/mfd/aspeed-lpc.example.dts:30.35-36.15: > Warning (unique_unit_address): /example-0/lpc@1e789000/lpc-ctrl@80: > duplicate unit-address (also used in node > /example-0/lpc@1e789000/lpc-snoop@80) > Documentation/devicetree/bindings/mfd/aspeed-lpc.example.dt.yaml:0:0: > /example-0/lpc@1e789000/lpc-ctrl@80: failed to match any schema with > compatible: ['aspeed,ast2600-lpc-ctrl'] > Documentation/devicetree/bindings/mfd/aspeed-lpc.example.dt.yaml:0:0: > /example-0/lpc@1e789000/reset-controller@98: failed to match any schema > with compatible: ['aspeed,ast2600-lpc-reset'] > Documentation/devicetree/bindings/mfd/aspeed-lpc.example.dt.yaml:0:0: > /example-0/lpc@1e789000/lpc-snoop@80: failed to match any schema with > compatible: ['aspeed,ast2600-lpc-snoop'] > I also encountered this error locally. However, I couldn't find the root cause as these three compatible strings have been described in the same YAML file. Could you guys help to give me some hints to resolve this issue? Greatly appreciate that. > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/patch/1527193 > > This check can fail if there are any dependencies. The base for a patch series is > generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above error(s), > then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit. My dtschema & yamllint version: dtschema-2021.7 yamllint-1.26.3 Regards, Chiawei
On Mon, Sep 13, 2021 at 1:02 AM Chia-Wei Wang <chiawei_wang@aspeedtech.com> wrote: > > Convert the bindings of Aspeed LPC from text file into YAML schema. > > Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> > --- > .../devicetree/bindings/mfd/aspeed-lpc.txt | 157 --------------- > .../devicetree/bindings/mfd/aspeed-lpc.yaml | 187 ++++++++++++++++++ > 2 files changed, 187 insertions(+), 157 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml > > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > deleted file mode 100644 > index 936aa108eab4..000000000000 > --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > +++ /dev/null > @@ -1,157 +0,0 @@ > -====================================================================== > -Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller > -====================================================================== > - > -The LPC bus is a means to bridge a host CPU to a number of low-bandwidth > -peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The > -primary use case of the Aspeed LPC controller is as a slave on the bus > -(typically in a Baseboard Management Controller SoC), but under certain > -conditions it can also take the role of bus master. > - > -The LPC controller is represented as a multi-function device to account for the > -mix of functionality, which includes, but is not limited to: > - > -* An IPMI Block Transfer[2] Controller > - > -* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the > - physical properties of some LPC pins, configuration of serial IRQs, and > - APB-to-LPC bridging amonst other functions. > - > -* An LPC Host Interface Controller: Manages functions exposed to the host such > - as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART > - management and bus snoop configuration. > - > -* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom > - hardware management protocols for handover between the host and baseboard > - management controller. > - > -Additionally the state of the LPC controller influences the pinmux > -configuration, therefore the host portion of the controller is exposed as a > -syscon as a means to arbitrate access. > - > -[0] http://www.intel.com/design/chipsets/industry/25128901.pdf > -[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4 > -[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf > -[3] https://en.wikipedia.org/wiki/Super_I/O > - > -Required properties > -=================== > - > -- compatible: One of: > - "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon" > - "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon" > - "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon" > - > -- reg: contains the physical address and length values of the Aspeed > - LPC memory region. > - > -- #address-cells: <1> > -- #size-cells: <1> > -- ranges: Maps 0 to the physical address and length of the LPC memory > - region > - > -Example: > - > -lpc: lpc@1e789000 { > - compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; > - reg = <0x1e789000 0x1000>; > - > - #address-cells = <1>; > - #size-cells = <1>; > - ranges = <0x0 0x1e789000 0x1000>; > - > - lpc_snoop: lpc-snoop@0 { > - compatible = "aspeed,ast2600-lpc-snoop"; > - reg = <0x0 0x80>; > - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; > - snoop-ports = <0x80>; > - }; > -}; > - > - > -LPC Host Interface Controller > -------------------- > - > -The LPC Host Interface Controller manages functions exposed to the host such as > -LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART > -management and bus snoop configuration. > - > -Required properties: > - > -- compatible: One of: > - "aspeed,ast2400-lpc-ctrl"; > - "aspeed,ast2500-lpc-ctrl"; > - "aspeed,ast2600-lpc-ctrl"; > - > -- reg: contains offset/length values of the host interface controller > - memory regions > - > -- clocks: contains a phandle to the syscon node describing the clocks. > - There should then be one cell representing the clock to use > - > -Optional properties: > - > -- memory-region: A phandle to a reserved_memory region to be used for the LPC > - to AHB mapping > - > -- flash: A phandle to the SPI flash controller containing the flash to > - be exposed over the LPC to AHB mapping > - > -Example: > - > -lpc_ctrl: lpc-ctrl@80 { > - compatible = "aspeed,ast2500-lpc-ctrl"; > - reg = <0x80 0x80>; > - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; > - memory-region = <&flash_memory>; > - flash = <&spi>; > -}; > - > -LPC Host Controller > -------------------- > - > -The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour > -between the host and the baseboard management controller. The registers exist > -in the "host" portion of the Aspeed LPC controller, which must be the parent of > -the LPC host controller node. > - > -Required properties: > - > -- compatible: One of: > - "aspeed,ast2400-lhc"; > - "aspeed,ast2500-lhc"; > - "aspeed,ast2600-lhc"; > - > -- reg: contains offset/length values of the LHC memory regions. In the > - AST2400 and AST2500 there are two regions. > - > -Example: > - > -lhc: lhc@a0 { > - compatible = "aspeed,ast2500-lhc"; > - reg = <0xa0 0x24 0xc8 0x8>; > -}; > - > -LPC reset control > ------------------ > - > -The UARTs present in the ASPEED SoC can have their resets tied to the reset > -state of the LPC bus. Some systems may chose to modify this configuration. > - > -Required properties: > - > - - compatible: One of: > - "aspeed,ast2600-lpc-reset"; > - "aspeed,ast2500-lpc-reset"; > - "aspeed,ast2400-lpc-reset"; > - > - - reg: offset and length of the IP in the LHC memory region > - - #reset-controller indicates the number of reset cells expected > - > -Example: > - > -lpc_reset: reset-controller@98 { > - compatible = "aspeed,ast2500-lpc-reset"; > - reg = <0x98 0x4>; > - #reset-cells = <1>; > -}; > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml > new file mode 100644 > index 000000000000..4e3862cf2a4b > --- /dev/null > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml > @@ -0,0 +1,187 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# # Copyright (c) 2021 Aspeed Tehchnology Inc. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Aspeed Low Pin Count (LPC) Bus Controller > + > +maintainers: > + - Andrew Jeffery <andrew@aj.id.au> > + - Chia-Wei Wang <chiawei_wang@aspeedtech.com> > + > +description: > + The LPC bus is a means to bridge a host CPU to a number of low-bandwidth > + peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The > + primary use case of the Aspeed LPC controller is as a slave on the bus > + (typically in a Baseboard Management Controller SoC), but under certain > + conditions it can also take the role of bus master. > + > + The LPC controller is represented as a multi-function device to account for the > + mix of functionality, which includes, but is not limited to > + > + * An IPMI Block Transfer[2] Controller > + > + * An LPC Host Interface Controller manages functions exposed to the host such > + as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART > + management and bus snoop configuration. > + > + * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom > + hardware management protocols for handover between the host and baseboard > + management controller. > + > + Additionally the state of the LPC controller influences the pinmux > + configuration, therefore the host portion of the controller is exposed as a > + syscon as a means to arbitrate access. > + > +properties: > + compatible: > + items: > + - enum: > + - aspeed,ast2400-lpc-v2 > + - aspeed,ast2500-lpc-v2 > + - aspeed,ast2600-lpc-v2 > + - const: simple-mfd > + - const: syscon > + > + reg: > + maxItems: 1 > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 1 > + > + ranges: true > + > +patternProperties: > + "^lpc-ctrl@[0-9a-f]+$": > + type: object > + > + description: > + The LPC Host Interface Controller manages functions exposed to the host such as > + LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management > + and bus snoop configuration. > + > + properties: > + comptabile: typo here. This is the source of your warnings. Rob
> From: Rob Herring <robh+dt@kernel.org> > Sent: Tuesday, September 14, 2021 8:28 PM > > On Mon, Sep 13, 2021 at 1:02 AM Chia-Wei Wang > <chiawei_wang@aspeedtech.com> wrote: > > > > Convert the bindings of Aspeed LPC from text file into YAML schema. > > > > Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> > > --- > > .../devicetree/bindings/mfd/aspeed-lpc.txt | 157 --------------- > > .../devicetree/bindings/mfd/aspeed-lpc.yaml | 187 > ++++++++++++++++++ > > 2 files changed, 187 insertions(+), 157 deletions(-) delete mode > > 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > > create mode 100644 > > Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml > > > > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > > b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > > deleted file mode 100644 > > index 936aa108eab4..000000000000 > > --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > > +++ /dev/null > > @@ -1,157 +0,0 @@ > > > > +patternProperties: > > + "^lpc-ctrl@[0-9a-f]+$": > > + type: object > > + > > + description: > > + The LPC Host Interface Controller manages functions exposed to the > host such as > > + LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, > UART management > > + and bus snoop configuration. > > + > > + properties: > > + comptabile: > > typo here. This is the source of your warnings. Thanks! Sorry for making this typo. Will keep in mind to check the spelling in the future. A v5 patch will be sent to fix these warning. Regards, Chiawei
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt deleted file mode 100644 index 936aa108eab4..000000000000 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ /dev/null @@ -1,157 +0,0 @@ -====================================================================== -Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller -====================================================================== - -The LPC bus is a means to bridge a host CPU to a number of low-bandwidth -peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The -primary use case of the Aspeed LPC controller is as a slave on the bus -(typically in a Baseboard Management Controller SoC), but under certain -conditions it can also take the role of bus master. - -The LPC controller is represented as a multi-function device to account for the -mix of functionality, which includes, but is not limited to: - -* An IPMI Block Transfer[2] Controller - -* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the - physical properties of some LPC pins, configuration of serial IRQs, and - APB-to-LPC bridging amonst other functions. - -* An LPC Host Interface Controller: Manages functions exposed to the host such - as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART - management and bus snoop configuration. - -* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom - hardware management protocols for handover between the host and baseboard - management controller. - -Additionally the state of the LPC controller influences the pinmux -configuration, therefore the host portion of the controller is exposed as a -syscon as a means to arbitrate access. - -[0] http://www.intel.com/design/chipsets/industry/25128901.pdf -[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4 -[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf -[3] https://en.wikipedia.org/wiki/Super_I/O - -Required properties -=================== - -- compatible: One of: - "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon" - "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon" - "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon" - -- reg: contains the physical address and length values of the Aspeed - LPC memory region. - -- #address-cells: <1> -- #size-cells: <1> -- ranges: Maps 0 to the physical address and length of the LPC memory - region - -Example: - -lpc: lpc@1e789000 { - compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; - reg = <0x1e789000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e789000 0x1000>; - - lpc_snoop: lpc-snoop@0 { - compatible = "aspeed,ast2600-lpc-snoop"; - reg = <0x0 0x80>; - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - snoop-ports = <0x80>; - }; -}; - - -LPC Host Interface Controller -------------------- - -The LPC Host Interface Controller manages functions exposed to the host such as -LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART -management and bus snoop configuration. - -Required properties: - -- compatible: One of: - "aspeed,ast2400-lpc-ctrl"; - "aspeed,ast2500-lpc-ctrl"; - "aspeed,ast2600-lpc-ctrl"; - -- reg: contains offset/length values of the host interface controller - memory regions - -- clocks: contains a phandle to the syscon node describing the clocks. - There should then be one cell representing the clock to use - -Optional properties: - -- memory-region: A phandle to a reserved_memory region to be used for the LPC - to AHB mapping - -- flash: A phandle to the SPI flash controller containing the flash to - be exposed over the LPC to AHB mapping - -Example: - -lpc_ctrl: lpc-ctrl@80 { - compatible = "aspeed,ast2500-lpc-ctrl"; - reg = <0x80 0x80>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - memory-region = <&flash_memory>; - flash = <&spi>; -}; - -LPC Host Controller -------------------- - -The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour -between the host and the baseboard management controller. The registers exist -in the "host" portion of the Aspeed LPC controller, which must be the parent of -the LPC host controller node. - -Required properties: - -- compatible: One of: - "aspeed,ast2400-lhc"; - "aspeed,ast2500-lhc"; - "aspeed,ast2600-lhc"; - -- reg: contains offset/length values of the LHC memory regions. In the - AST2400 and AST2500 there are two regions. - -Example: - -lhc: lhc@a0 { - compatible = "aspeed,ast2500-lhc"; - reg = <0xa0 0x24 0xc8 0x8>; -}; - -LPC reset control ------------------ - -The UARTs present in the ASPEED SoC can have their resets tied to the reset -state of the LPC bus. Some systems may chose to modify this configuration. - -Required properties: - - - compatible: One of: - "aspeed,ast2600-lpc-reset"; - "aspeed,ast2500-lpc-reset"; - "aspeed,ast2400-lpc-reset"; - - - reg: offset and length of the IP in the LHC memory region - - #reset-controller indicates the number of reset cells expected - -Example: - -lpc_reset: reset-controller@98 { - compatible = "aspeed,ast2500-lpc-reset"; - reg = <0x98 0x4>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml new file mode 100644 index 000000000000..4e3862cf2a4b --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# # Copyright (c) 2021 Aspeed Tehchnology Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed Low Pin Count (LPC) Bus Controller + +maintainers: + - Andrew Jeffery <andrew@aj.id.au> + - Chia-Wei Wang <chiawei_wang@aspeedtech.com> + +description: + The LPC bus is a means to bridge a host CPU to a number of low-bandwidth + peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The + primary use case of the Aspeed LPC controller is as a slave on the bus + (typically in a Baseboard Management Controller SoC), but under certain + conditions it can also take the role of bus master. + + The LPC controller is represented as a multi-function device to account for the + mix of functionality, which includes, but is not limited to + + * An IPMI Block Transfer[2] Controller + + * An LPC Host Interface Controller manages functions exposed to the host such + as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART + management and bus snoop configuration. + + * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom + hardware management protocols for handover between the host and baseboard + management controller. + + Additionally the state of the LPC controller influences the pinmux + configuration, therefore the host portion of the controller is exposed as a + syscon as a means to arbitrate access. + +properties: + compatible: + items: + - enum: + - aspeed,ast2400-lpc-v2 + - aspeed,ast2500-lpc-v2 + - aspeed,ast2600-lpc-v2 + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^lpc-ctrl@[0-9a-f]+$": + type: object + + description: + The LPC Host Interface Controller manages functions exposed to the host such as + LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management + and bus snoop configuration. + + properties: + comptabile: + items: + - enum: + - aspeed,ast2400-lpc-ctrl + - aspeed,ast2500-lpc-ctrl + - aspeed,ast2600-lpc-ctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + memory-region: + $ref: /schemas/types.yaml#/definitions/phandle + description: A reserved_memory region to be used for the LPC to AHB mapping + + flash: + $ref: /schemas/types.yaml#/definitions/phandle + description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping + + required: + - compatible + - clocks + + "^reset-controller@[0-9a-f]+$": + type: object + + description: + The UARTs present in the ASPEED SoC can have their resets tied to the reset + state of the LPC bus. Some systems may chose to modify this configuration + + properties: + comptabile: + items: + - enum: + - aspeed,ast2400-lpc-reset + - aspeed,ast2500-lpc-reset + - aspeed,ast2600-lpc-reset + + reg: + maxItems: 1 + + required: + - compatible + + "^lpc-snoop@[0-9a-f]+$": + type: object + + description: + The LPC snoop interface allows the BMC to listen on and record the data + bytes written by the Host to the targeted LPC I/O pots. + + properties: + comptabile: + items: + - enum: + - aspeed,ast2400-lpc-snoop + - aspeed,ast2500-lpc-snoop + - aspeed,ast2600-lpc-snoop + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + snoop-ports: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: The LPC I/O ports to snoop + + required: + - compatible + - interrupts + - snoop-ports + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/ast2600-clock.h> + + lpc: lpc@1e789000 { + compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; + reg = <0x1e789000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + lpc_ctrl: lpc-ctrl@80 { + compatible = "aspeed,ast2600-lpc-ctrl"; + reg = <0x80 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + memory-region = <&flash_memory>; + flash = <&spi>; + }; + + lpc_reset: reset-controller@98 { + compatible = "aspeed,ast2600-lpc-reset"; + reg = <0x98 0x4>; + #reset-cells = <1>; + }; + + lpc_snoop: lpc-snoop@80 { + compatible = "aspeed,ast2600-lpc-snoop"; + reg = <0x80 0x80>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + snoop-ports = <0x80>; + }; + };
Convert the bindings of Aspeed LPC from text file into YAML schema. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> --- .../devicetree/bindings/mfd/aspeed-lpc.txt | 157 --------------- .../devicetree/bindings/mfd/aspeed-lpc.yaml | 187 ++++++++++++++++++ 2 files changed, 187 insertions(+), 157 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml