diff mbox series

[v2,2/2] power: supply: max17042_battery: Prevent int underflow in set_soc_threshold

Message ID 20210914121806.1301131-2-sebastian.krzyszkowiak@puri.sm (mailing list archive)
State Not Applicable, archived
Headers show
Series [v2,1/2] power: supply: max17042_battery: Clear status bits in interrupt handler | expand

Commit Message

Sebastian Krzyszkowiak Sept. 14, 2021, 12:18 p.m. UTC
max17042_set_soc_threshold gets called with offset set to 1, which means
that minimum threshold value would underflow once SOC got down to 0,
causing invalid alerts from the gauge.

Fixes: e5f3872d2044 ("max17042: Add support for signalling change in SOC")
Cc: <stable@vger.kernel.org>
Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>
---
v2: added commit description
---
 drivers/power/supply/max17042_battery.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Krzysztof Kozlowski Sept. 16, 2021, 10:26 a.m. UTC | #1
On 14/09/2021 14:18, Sebastian Krzyszkowiak wrote:
> max17042_set_soc_threshold gets called with offset set to 1, which means
> that minimum threshold value would underflow once SOC got down to 0,
> causing invalid alerts from the gauge.
> 
> Fixes: e5f3872d2044 ("max17042: Add support for signalling change in SOC")
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>
> ---
> v2: added commit description
> ---


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>


Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/drivers/power/supply/max17042_battery.c b/drivers/power/supply/max17042_battery.c
index da78ffe6a3ec..189c1979bc7b 100644
--- a/drivers/power/supply/max17042_battery.c
+++ b/drivers/power/supply/max17042_battery.c
@@ -857,7 +857,8 @@  static void max17042_set_soc_threshold(struct max17042_chip *chip, u16 off)
 	regmap_read(map, MAX17042_RepSOC, &soc);
 	soc >>= 8;
 	soc_tr = (soc + off) << 8;
-	soc_tr |= (soc - off);
+	if (off < soc)
+		soc_tr |= soc - off;
 	regmap_write(map, MAX17042_SALRT_Th, soc_tr);
 }