| Message ID | 20210922073834.21304-2-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | [1/2] clk: renesas: r9a07g044: Add IA55_CLK and DMAC_ACLK | expand |
Hello! On 22.09.2021 10:38, Biju Das wrote: > As per RZ/G2L HW(Rev.0.50) manual, clock monitor register value > 0 means clock is not supplied and 1 means clock is supplied. > This patch fixes the issue by removing the inverted logic. > > Fixing the above, triggered following 2 issues > > 1) GIC interrupts don't work if we disable IA55_CLK and DMAC_ACLK. > Fixed this issue by adding these clocks as critical clocks. > > 2) DMA is not working, since the DMA driver is not turning on DMAC_PCLK. > So will provide a fix in the DMA driver to turn on DMA_PCLK. > > Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > drivers/clk/renesas/rzg2l-cpg.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c > index 3b3b2c3347f3..3e32a858b852 100644 > --- a/drivers/clk/renesas/rzg2l-cpg.c > +++ b/drivers/clk/renesas/rzg2l-cpg.c > @@ -391,7 +391,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw) > > value = readl(priv->base + CLK_MON_R(clock->off)); > > - return !(value & bitmask); > + return (value & bitmask); Parens not needed anymore... [...] MBR, Sergei
Hi Sergei, Thanks for feedback. > Subject: Re: [PATCH 2/2] clk: renesas: rzg2l: Fix clk status function > > Hello! > > On 22.09.2021 10:38, Biju Das wrote: > > > As per RZ/G2L HW(Rev.0.50) manual, clock monitor register value > > 0 means clock is not supplied and 1 means clock is supplied. > > This patch fixes the issue by removing the inverted logic. > > > > Fixing the above, triggered following 2 issues > > > > 1) GIC interrupts don't work if we disable IA55_CLK and DMAC_ACLK. > > Fixed this issue by adding these clocks as critical clocks. > > > > 2) DMA is not working, since the DMA driver is not turning on DMAC_PCLK. > > So will provide a fix in the DMA driver to turn on DMA_PCLK. > > > > Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L > > SoC") > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > drivers/clk/renesas/rzg2l-cpg.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/clk/renesas/rzg2l-cpg.c > > b/drivers/clk/renesas/rzg2l-cpg.c index 3b3b2c3347f3..3e32a858b852 > > 100644 > > --- a/drivers/clk/renesas/rzg2l-cpg.c > > +++ b/drivers/clk/renesas/rzg2l-cpg.c > > @@ -391,7 +391,7 @@ static int rzg2l_mod_clock_is_enabled(struct > > clk_hw *hw) > > > > value = readl(priv->base + CLK_MON_R(clock->off)); > > > > - return !(value & bitmask); > > + return (value & bitmask); > > Parens not needed anymore... Good catch. Will send V2. Regards, Biju
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 3b3b2c3347f3..3e32a858b852 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -391,7 +391,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw) value = readl(priv->base + CLK_MON_R(clock->off)); - return !(value & bitmask); + return (value & bitmask); } static const struct clk_ops rzg2l_mod_clock_ops = {
As per RZ/G2L HW(Rev.0.50) manual, clock monitor register value 0 means clock is not supplied and 1 means clock is supplied. This patch fixes the issue by removing the inverted logic. Fixing the above, triggered following 2 issues 1) GIC interrupts don't work if we disable IA55_CLK and DMAC_ACLK. Fixed this issue by adding these clocks as critical clocks. 2) DMA is not working, since the DMA driver is not turning on DMAC_PCLK. So will provide a fix in the DMA driver to turn on DMA_PCLK. Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/renesas/rzg2l-cpg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)