| Message ID | 20210713232510.3057750-1-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | clk: meson8b: video clock tree fixes and making it mutable | expand |
On Wed 14 Jul 2021 at 01:25, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > The first two patches in this series are small fixes before we can > actually make the video clock tree mutable. One patch adds > CLK_SET_RATE_NO_REPARENT for better rate control and the other adds > a missing clock gate. > > The third and fourth patch are targeting the HDMI PLL. Add the known > working M/N combinations. Also this PLL has some special "doubling" > setting, which is calculated like this: > OUTPUT = (IN * M / N + FRAC) * 2 > Since not all register bits are known we use a copy of the 2970/2975MHz > magic register values from the vendor driver. > > The fifth patch makes the clocks in the video clock tree mutable. The > final patch in this series exports the clocks needed for rate control. > > For reference, this is the .dts definition for the Meson8b VPU. The > code for the VPU driver is unfortunately not ready for upstreaming yet. > However, I have tested with all resolutions my monitor supports and the > clock settings are all applied correctly. > vpu: vpu@100000 { > compatible = "amlogic,meson8b-vpu"; > > reg = <0x100000 0x10000>; > reg-names = "vpu"; > > interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; > > amlogic,canvas = <&canvas>; > amlogic,hhi-sysctrl = <&hhi>; > > /* > * The VCLK{,2}_IN path always needs to derived from > * the CLKID_VID_PLL_FINAL_DIV so other clocks like > * MPLL1 are not used (MPLL1 is reserved for audio > * purposes). > */ > assigned-clocks = <&clkc CLKID_VCLK_IN_SEL>, > <&clkc CLKID_VCLK2_IN_SEL>; > assigned-clock-parents = <&clkc CLKID_VID_PLL_FINAL_DIV>, > <&clkc CLKID_VID_PLL_FINAL_DIV>; > > clocks = <&clkc CLKID_VPU_INTR>, > <&clkc CLKID_HDMI_INTR_SYNC>, > <&clkc CLKID_GCLK_VENCI_INT>, > <&clkc CLKID_HDMI_PLL_HDMI_OUT>, > <&clkc CLKID_HDMI_TX_PIXEL>, > <&clkc CLKID_CTS_ENCP>, > <&clkc CLKID_CTS_ENCI>, > <&clkc CLKID_CTS_ENCT>, > <&clkc CLKID_CTS_ENCL>, > <&clkc CLKID_CTS_VDAC0>; > clock-names = "vpu_intr", > "hdmi_intr_sync", > "venci_int", > "tmds", > "hdmi_tx_pixel", > "cts_encp", > "cts_enci", > "cts_enct", > "cts_encl", > "cts_vdac0"; > > resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>, > <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>, > <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>, > <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>; > reset-names = "vid_pll_pre", > "vid_pll_post", > "vid_pll_soft_pre", > "vid_pll_soft_post"; > > power-domains = <&pwrc PWRC_MESON8_VPU_ID>; > > nvmem-cells = <&cvbs_trimming>; > nvmem-cell-names = "cvbs_trimming"; > > #address-cells = <1>; > #size-cells = <0>; > > #sound-dai-cells = <0>; > sound-name-prefix = "HDMITX"; > > /* CVBS VDAC output port */ > cvbs_vdac_port: port@0 { > reg = <0>; > }; > > /* HDMI-TX output port */ > hdmi_tx_port: port@1 { > reg = <1>; > > hdmi_tx_out: endpoint { > remote-endpoint = <&hdmi_tx_in>; > }; > }; > }; > > > Martin Blumenstingl (6): > clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel > clk: meson: meson8b: Add the vid_pll_lvds_en gate clock > clk: meson: meson8b: Add the HDMI PLL M/N parameters > clk: meson: meson8b: Initialize the HDMI PLL registers > clk: meson: meson8b: Make the video clock trees mutable > clk: meson: meson8b: Export the video clocks > > drivers/clk/meson/meson8b.c | 163 +++++++++++++++++------ > drivers/clk/meson/meson8b.h | 26 ++-- > include/dt-bindings/clock/meson8b-clkc.h | 10 ++ > 3 files changed, 143 insertions(+), 56 deletions(-) Applied, Thx
The first two patches in this series are small fixes before we can actually make the video clock tree mutable. One patch adds CLK_SET_RATE_NO_REPARENT for better rate control and the other adds a missing clock gate. The third and fourth patch are targeting the HDMI PLL. Add the known working M/N combinations. Also this PLL has some special "doubling" setting, which is calculated like this: OUTPUT = (IN * M / N + FRAC) * 2 Since not all register bits are known we use a copy of the 2970/2975MHz magic register values from the vendor driver. The fifth patch makes the clocks in the video clock tree mutable. The final patch in this series exports the clocks needed for rate control. For reference, this is the .dts definition for the Meson8b VPU. The code for the VPU driver is unfortunately not ready for upstreaming yet. However, I have tested with all resolutions my monitor supports and the clock settings are all applied correctly. vpu: vpu@100000 { compatible = "amlogic,meson8b-vpu"; reg = <0x100000 0x10000>; reg-names = "vpu"; interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; amlogic,canvas = <&canvas>; amlogic,hhi-sysctrl = <&hhi>; /* * The VCLK{,2}_IN path always needs to derived from * the CLKID_VID_PLL_FINAL_DIV so other clocks like * MPLL1 are not used (MPLL1 is reserved for audio * purposes). */ assigned-clocks = <&clkc CLKID_VCLK_IN_SEL>, <&clkc CLKID_VCLK2_IN_SEL>; assigned-clock-parents = <&clkc CLKID_VID_PLL_FINAL_DIV>, <&clkc CLKID_VID_PLL_FINAL_DIV>; clocks = <&clkc CLKID_VPU_INTR>, <&clkc CLKID_HDMI_INTR_SYNC>, <&clkc CLKID_GCLK_VENCI_INT>, <&clkc CLKID_HDMI_PLL_HDMI_OUT>, <&clkc CLKID_HDMI_TX_PIXEL>, <&clkc CLKID_CTS_ENCP>, <&clkc CLKID_CTS_ENCI>, <&clkc CLKID_CTS_ENCT>, <&clkc CLKID_CTS_ENCL>, <&clkc CLKID_CTS_VDAC0>; clock-names = "vpu_intr", "hdmi_intr_sync", "venci_int", "tmds", "hdmi_tx_pixel", "cts_encp", "cts_enci", "cts_enct", "cts_encl", "cts_vdac0"; resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>, <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>, <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>, <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>; reset-names = "vid_pll_pre", "vid_pll_post", "vid_pll_soft_pre", "vid_pll_soft_post"; power-domains = <&pwrc PWRC_MESON8_VPU_ID>; nvmem-cells = <&cvbs_trimming>; nvmem-cell-names = "cvbs_trimming"; #address-cells = <1>; #size-cells = <0>; #sound-dai-cells = <0>; sound-name-prefix = "HDMITX"; /* CVBS VDAC output port */ cvbs_vdac_port: port@0 { reg = <0>; }; /* HDMI-TX output port */ hdmi_tx_port: port@1 { reg = <1>; hdmi_tx_out: endpoint { remote-endpoint = <&hdmi_tx_in>; }; }; }; Martin Blumenstingl (6): clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel clk: meson: meson8b: Add the vid_pll_lvds_en gate clock clk: meson: meson8b: Add the HDMI PLL M/N parameters clk: meson: meson8b: Initialize the HDMI PLL registers clk: meson: meson8b: Make the video clock trees mutable clk: meson: meson8b: Export the video clocks drivers/clk/meson/meson8b.c | 163 +++++++++++++++++------ drivers/clk/meson/meson8b.h | 26 ++-- include/dt-bindings/clock/meson8b-clkc.h | 10 ++ 3 files changed, 143 insertions(+), 56 deletions(-)