| Message ID | 20210923140813.13541-19-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | Add Gigabit Ethernet driver support | expand |
| Context | Check | Description |
|---|---|---|
| netdev/cover_letter | success | Link |
| netdev/fixes_present | success | Link |
| netdev/patch_count | fail | Series longer than 15 patches |
| netdev/tree_selection | success | Guessed tree name to be net-next |
| netdev/subject_prefix | warning | Target tree name not specified in the subject |
| netdev/cc_maintainers | success | CCed 10 of 10 maintainers |
| netdev/source_inline | success | Was 0 now: 0 |
| netdev/verify_signedoff | success | Link |
| netdev/module_param | success | Was 0 now: 0 |
| netdev/build_32bit | success | Errors and warnings before: 0 this patch: 0 |
| netdev/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| netdev/verify_fixes | success | Link |
| netdev/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 118 lines checked |
| netdev/build_allmodconfig_warn | success | Errors and warnings before: 0 this patch: 0 |
| netdev/header_inline | success | Link |
On 9/23/21 5:08 PM, Biju Das wrote: > This patch adds set_feature support for RZ/G2L. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > drivers/net/ethernet/renesas/ravb.h | 32 ++++++++++++++ > drivers/net/ethernet/renesas/ravb_main.c | 56 +++++++++++++++++++++++- > 2 files changed, 87 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h > index d42e8ea981df..2275f27c0672 100644 > --- a/drivers/net/ethernet/renesas/ravb.h > +++ b/drivers/net/ethernet/renesas/ravb.h > @@ -209,6 +209,8 @@ enum ravb_reg { > CXR56 = 0x0770, /* Documented for RZ/G2L only */ > MAFCR = 0x0778, > CSR0 = 0x0800, /* Documented for RZ/G2L only */ > + CSR1 = 0x0804, /* Documented for RZ/G2L only */ > + CSR2 = 0x0808, /* Documented for RZ/G2L only */ These are the TOE regs (CSR0 included), they only exist on RZ/G2L, no? [...] > @@ -978,6 +980,36 @@ enum CSR0_BIT { > CSR0_RPE = 0x00000020, > }; > *enum* CSR0_BIT should be here (as we concluded). > +enum CSR1_BIT { [...] > diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c > index 72aea5875bc5..641ae5553b64 100644 > --- a/drivers/net/ethernet/renesas/ravb_main.c > +++ b/drivers/net/ethernet/renesas/ravb_main.c [...] > @@ -2290,7 +2308,38 @@ static void ravb_set_rx_csum(struct net_device *ndev, bool enable) > static int ravb_set_features_rgeth(struct net_device *ndev, > netdev_features_t features) > { > - /* Place holder */ > + netdev_features_t changed = features ^ ndev->features; > + unsigned int reg; u32 reg; > + int error; > + > + reg = ravb_read(ndev, CSR0); ... as this function returns u32. > + > + ravb_write(ndev, reg & ~(CSR0_RPE | CSR0_TPE), CSR0); > + error = ravb_wait(ndev, CSR0, CSR0_RPE | CSR0_TPE, 0); > + if (error) { > + ravb_write(ndev, reg, CSR0); > + return error; > + } > + > + if (changed & NETIF_F_RXCSUM) { > + if (features & NETIF_F_RXCSUM) > + ravb_write(ndev, CSR2_ALL, CSR2); > + else > + ravb_write(ndev, 0, CSR2); > + } > + > + if (changed & NETIF_F_HW_CSUM) { > + if (features & NETIF_F_HW_CSUM) { > + ravb_write(ndev, CSR1_ALL, CSR1); > + ndev->features |= NETIF_F_CSUM_MASK; Hm, I don't understand this... it would be nice if someone knowledgeable about the offloads would look at this... Although, without the register documentation it's possibly vain... > + } else { > + ravb_write(ndev, 0, CSR1); > + } > + } > + ravb_write(ndev, reg, CSR0); > + > + ndev->features = features; > + > return 0; > } > > @@ -2432,6 +2481,11 @@ static const struct ravb_hw_info rgeth_hw_info = { > .set_feature = ravb_set_features_rgeth, > .dmac_init = ravb_dmac_init_rgeth, > .emac_init = ravb_emac_init_rgeth, > + .net_hw_features = (NETIF_F_HW_CSUM | NETIF_F_RXCSUM), > + .gstrings_stats = ravb_gstrings_stats_rgeth, > + .gstrings_size = sizeof(ravb_gstrings_stats_rgeth), > + .stats_len = ARRAY_SIZE(ravb_gstrings_stats_rgeth), These seem unrelated, couldn't it be moved to a spearate patch? > + .max_rx_len = RGETH_RX_BUFF_MAX + RAVB_ALIGN - 1, This seems unrelsated and misplaced too. [...] MBR, Sergey
Hi Sergei, Thanks for the feedback. > Subject: Re: [RFC/PATCH 18/18] ravb: Add set_feature support for RZ/G2L > > On 9/23/21 5:08 PM, Biju Das wrote: > > > This patch adds set_feature support for RZ/G2L. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > drivers/net/ethernet/renesas/ravb.h | 32 ++++++++++++++ > > drivers/net/ethernet/renesas/ravb_main.c | 56 > > +++++++++++++++++++++++- > > 2 files changed, 87 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/net/ethernet/renesas/ravb.h > > b/drivers/net/ethernet/renesas/ravb.h > > index d42e8ea981df..2275f27c0672 100644 > > --- a/drivers/net/ethernet/renesas/ravb.h > > +++ b/drivers/net/ethernet/renesas/ravb.h > > @@ -209,6 +209,8 @@ enum ravb_reg { > > CXR56 = 0x0770, /* Documented for RZ/G2L only */ > > MAFCR = 0x0778, > > CSR0 = 0x0800, /* Documented for RZ/G2L only */ > > + CSR1 = 0x0804, /* Documented for RZ/G2L only */ > > + CSR2 = 0x0808, /* Documented for RZ/G2L only */ > > These are the TOE regs (CSR0 included), they only exist on RZ/G2L, no? See just one line above you can see CSR0 registers and comments on the right clearly mentions "/* Documented for RZ/G2L only */ OK will do CSR0 initialisation as part of this patch instead of patch #10. > [...] > > @@ -978,6 +980,36 @@ enum CSR0_BIT { > > CSR0_RPE = 0x00000020, > > }; > > > > *enum* CSR0_BIT should be here (as we concluded). It is already there. See above. As discussed above it will be moved from patch #10 to here. > > > +enum CSR1_BIT { > [...] > > diff --git a/drivers/net/ethernet/renesas/ravb_main.c > > b/drivers/net/ethernet/renesas/ravb_main.c > > index 72aea5875bc5..641ae5553b64 100644 > > --- a/drivers/net/ethernet/renesas/ravb_main.c > > +++ b/drivers/net/ethernet/renesas/ravb_main.c > [...] > > @@ -2290,7 +2308,38 @@ static void ravb_set_rx_csum(struct net_device > > *ndev, bool enable) static int ravb_set_features_rgeth(struct > net_device *ndev, > > netdev_features_t features) > > { > > - /* Place holder */ > > + netdev_features_t changed = features ^ ndev->features; > > + unsigned int reg; > > u32 reg; > > > + int error; > > + > > + reg = ravb_read(ndev, CSR0); > > ... as this function returns u32. > > > + > > + ravb_write(ndev, reg & ~(CSR0_RPE | CSR0_TPE), CSR0); > > + error = ravb_wait(ndev, CSR0, CSR0_RPE | CSR0_TPE, 0); > > + if (error) { > > + ravb_write(ndev, reg, CSR0); > > + return error; > > + } > > + > > + if (changed & NETIF_F_RXCSUM) { > > + if (features & NETIF_F_RXCSUM) > > + ravb_write(ndev, CSR2_ALL, CSR2); > > + else > > + ravb_write(ndev, 0, CSR2); > > + } > > + > > + if (changed & NETIF_F_HW_CSUM) { > > + if (features & NETIF_F_HW_CSUM) { > > + ravb_write(ndev, CSR1_ALL, CSR1); > > + ndev->features |= NETIF_F_CSUM_MASK; > > Hm, I don't understand this... it would be nice if someone > knowledgeable about the offloads would look at this... Although, without > the register documentation it's possibly vain... > > > + } else { > > + ravb_write(ndev, 0, CSR1); > > + } > > + } > > + ravb_write(ndev, reg, CSR0); > > + > > + ndev->features = features; > > + > > return 0; > > } > > > > @@ -2432,6 +2481,11 @@ static const struct ravb_hw_info rgeth_hw_info = > { > > .set_feature = ravb_set_features_rgeth, > > .dmac_init = ravb_dmac_init_rgeth, > > .emac_init = ravb_emac_init_rgeth, > > + .net_hw_features = (NETIF_F_HW_CSUM | NETIF_F_RXCSUM), > > + .gstrings_stats = ravb_gstrings_stats_rgeth, > > + .gstrings_size = sizeof(ravb_gstrings_stats_rgeth), > > + .stats_len = ARRAY_SIZE(ravb_gstrings_stats_rgeth), > > These seem unrelated, couldn't it be moved to a spearate patch? Ok will split into 2. Adding set_feature support in first patch and stats in second patch. > > > + .max_rx_len = RGETH_RX_BUFF_MAX + RAVB_ALIGN - 1, > > This seems unrelsated and misplaced too. Agreed. It is a mistake. Will be taken care in next version. Regards, Biju > > [...] > > MBR, Sergey
> -----Original Message----- > From: Sergey Shtylyov <s.shtylyov@omp.ru> > Sent: 30 September 2021 21:39 > To: Biju Das <biju.das.jz@bp.renesas.com>; David S. Miller > <davem@davemloft.net>; Jakub Kicinski <kuba@kernel.org> > Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; > Andrew Lunn <andrew@lunn.ch>; Sergei Shtylyov <sergei.shtylyov@gmail.com>; > Geert Uytterhoeven <geert+renesas@glider.be>; Adam Ford > <aford173@gmail.com>; Yoshihiro Shimoda > <yoshihiro.shimoda.uh@renesas.com>; netdev@vger.kernel.org; linux-renesas- > soc@vger.kernel.org; Chris Paterson <Chris.Paterson2@renesas.com>; Biju > Das <biju.das@bp.renesas.com> > Subject: Re: [RFC/PATCH 18/18] ravb: Add set_feature support for RZ/G2L > > On 9/23/21 5:08 PM, Biju Das wrote: > > > This patch adds set_feature support for RZ/G2L. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > drivers/net/ethernet/renesas/ravb.h | 32 ++++++++++++++ > > drivers/net/ethernet/renesas/ravb_main.c | 56 > > +++++++++++++++++++++++- > > 2 files changed, 87 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/net/ethernet/renesas/ravb.h > > b/drivers/net/ethernet/renesas/ravb.h > > index d42e8ea981df..2275f27c0672 100644 > > --- a/drivers/net/ethernet/renesas/ravb.h > > +++ b/drivers/net/ethernet/renesas/ravb.h > > @@ -209,6 +209,8 @@ enum ravb_reg { > > CXR56 = 0x0770, /* Documented for RZ/G2L only */ > > MAFCR = 0x0778, > > CSR0 = 0x0800, /* Documented for RZ/G2L only */ > > + CSR1 = 0x0804, /* Documented for RZ/G2L only */ > > + CSR2 = 0x0808, /* Documented for RZ/G2L only */ > > These are the TOE regs (CSR0 included), they only exist on RZ/G2L, no? > > [...] > > @@ -978,6 +980,36 @@ enum CSR0_BIT { > > CSR0_RPE = 0x00000020, > > }; > > > > *enum* CSR0_BIT should be here (as we concluded). > > > +enum CSR1_BIT { > [...] > > diff --git a/drivers/net/ethernet/renesas/ravb_main.c > > b/drivers/net/ethernet/renesas/ravb_main.c > > index 72aea5875bc5..641ae5553b64 100644 > > --- a/drivers/net/ethernet/renesas/ravb_main.c > > +++ b/drivers/net/ethernet/renesas/ravb_main.c > [...] > > @@ -2290,7 +2308,38 @@ static void ravb_set_rx_csum(struct net_device > > *ndev, bool enable) static int ravb_set_features_rgeth(struct > net_device *ndev, > > netdev_features_t features) > > { > > - /* Place holder */ > > + netdev_features_t changed = features ^ ndev->features; > > + unsigned int reg; > > u32 reg; > > > + int error; > > + > > + reg = ravb_read(ndev, CSR0); > > ... as this function returns u32. > > > + > > + ravb_write(ndev, reg & ~(CSR0_RPE | CSR0_TPE), CSR0); > > + error = ravb_wait(ndev, CSR0, CSR0_RPE | CSR0_TPE, 0); > > + if (error) { > > + ravb_write(ndev, reg, CSR0); > > + return error; > > + } > > + > > + if (changed & NETIF_F_RXCSUM) { > > + if (features & NETIF_F_RXCSUM) > > + ravb_write(ndev, CSR2_ALL, CSR2); > > + else > > + ravb_write(ndev, 0, CSR2); > > + } > > + > > + if (changed & NETIF_F_HW_CSUM) { > > + if (features & NETIF_F_HW_CSUM) { > > + ravb_write(ndev, CSR1_ALL, CSR1); > > + ndev->features |= NETIF_F_CSUM_MASK; > > Hm, I don't understand this... it would be nice if someone > knowledgeable about the offloads would look at this... Although, without > the register documentation it's possibly vain... You can download the document from here [1] [1] https://www.renesas.com/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?language=en&r=1467981 Regards, Biju > > > + } else { > > + ravb_write(ndev, 0, CSR1); > > + } > > + } > > + ravb_write(ndev, reg, CSR0); > > + > > + ndev->features = features; > > + > > return 0; > > } > > > > @@ -2432,6 +2481,11 @@ static const struct ravb_hw_info rgeth_hw_info = > { > > .set_feature = ravb_set_features_rgeth, > > .dmac_init = ravb_dmac_init_rgeth, > > .emac_init = ravb_emac_init_rgeth, > > + .net_hw_features = (NETIF_F_HW_CSUM | NETIF_F_RXCSUM), > > + .gstrings_stats = ravb_gstrings_stats_rgeth, > > + .gstrings_size = sizeof(ravb_gstrings_stats_rgeth), > > + .stats_len = ARRAY_SIZE(ravb_gstrings_stats_rgeth), > > These seem unrelated, couldn't it be moved to a spearate patch? > > > + .max_rx_len = RGETH_RX_BUFF_MAX + RAVB_ALIGN - 1, > > This seems unrelsated and misplaced too. > > [...] > > MBR, Sergey
On 01.10.2021 9:53, Biju Das wrote: [...] >>> This patch adds set_feature support for RZ/G2L. >>> >>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> >>> --- >>> drivers/net/ethernet/renesas/ravb.h | 32 ++++++++++++++ >>> drivers/net/ethernet/renesas/ravb_main.c | 56 >>> +++++++++++++++++++++++- >>> 2 files changed, 87 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/net/ethernet/renesas/ravb.h >>> b/drivers/net/ethernet/renesas/ravb.h >>> index d42e8ea981df..2275f27c0672 100644 >>> --- a/drivers/net/ethernet/renesas/ravb.h >>> +++ b/drivers/net/ethernet/renesas/ravb.h >>> @@ -209,6 +209,8 @@ enum ravb_reg { >>> CXR56 = 0x0770, /* Documented for RZ/G2L only */ >>> MAFCR = 0x0778, >>> CSR0 = 0x0800, /* Documented for RZ/G2L only */ >>> + CSR1 = 0x0804, /* Documented for RZ/G2L only */ >>> + CSR2 = 0x0808, /* Documented for RZ/G2L only */ >> >> These are the TOE regs (CSR0 included), they only exist on RZ/G2L, no? > > See just one line above you can see CSR0 registers and comments on the right clearly > mentions "/* Documented for RZ/G2L only */ What I meant was commenting on them as /* RZ/GL2 only */ or some such. Sorry for not being clear enough. > OK will do CSR0 initialisation as part of this patch instead of patch #10. TIA! >> [...] >>> diff --git a/drivers/net/ethernet/renesas/ravb_main.c >>> b/drivers/net/ethernet/renesas/ravb_main.c >>> index 72aea5875bc5..641ae5553b64 100644 >>> --- a/drivers/net/ethernet/renesas/ravb_main.c >>> +++ b/drivers/net/ethernet/renesas/ravb_main.c >> [...] >>> @@ -2290,7 +2308,38 @@ static void ravb_set_rx_csum(struct net_device >>> *ndev, bool enable) static int ravb_set_features_rgeth(struct >> net_device *ndev, >>> netdev_features_t features) >>> { >>> - /* Place holder */ >>> + netdev_features_t changed = features ^ ndev->features; >>> + unsigned int reg; >> >> u32 reg; >> >>> + int error; >>> + >>> + reg = ravb_read(ndev, CSR0); >> >> ... as this function returns u32. I'm even suggesting to call this variable 'csr0'. [...] > Regards, > Biju MBR, Sergey
> Subject: Re: [RFC/PATCH 18/18] ravb: Add set_feature support for RZ/G2L > > On 01.10.2021 9:53, Biju Das wrote: > > [...] > >>> This patch adds set_feature support for RZ/G2L. > >>> > >>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > >>> --- > >>> drivers/net/ethernet/renesas/ravb.h | 32 ++++++++++++++ > >>> drivers/net/ethernet/renesas/ravb_main.c | 56 > >>> +++++++++++++++++++++++- > >>> 2 files changed, 87 insertions(+), 1 deletion(-) > >>> > >>> diff --git a/drivers/net/ethernet/renesas/ravb.h > >>> b/drivers/net/ethernet/renesas/ravb.h > >>> index d42e8ea981df..2275f27c0672 100644 > >>> --- a/drivers/net/ethernet/renesas/ravb.h > >>> +++ b/drivers/net/ethernet/renesas/ravb.h > >>> @@ -209,6 +209,8 @@ enum ravb_reg { > >>> CXR56 = 0x0770, /* Documented for RZ/G2L only */ > >>> MAFCR = 0x0778, > >>> CSR0 = 0x0800, /* Documented for RZ/G2L only */ > >>> + CSR1 = 0x0804, /* Documented for RZ/G2L only */ > >>> + CSR2 = 0x0808, /* Documented for RZ/G2L only */ > >> > >> These are the TOE regs (CSR0 included), they only exist on RZ/G2L, > no? > > > > See just one line above you can see CSR0 registers and comments on the > > right clearly mentions "/* Documented for RZ/G2L only */ > > What I meant was commenting on them as /* RZ/GL2 only */ or some such. > Sorry for not being clear enough. > OK. > > OK will do CSR0 initialisation as part of this patch instead of patch > #10. > > TIA! > > >> [...] > >>> diff --git a/drivers/net/ethernet/renesas/ravb_main.c > >>> b/drivers/net/ethernet/renesas/ravb_main.c > >>> index 72aea5875bc5..641ae5553b64 100644 > >>> --- a/drivers/net/ethernet/renesas/ravb_main.c > >>> +++ b/drivers/net/ethernet/renesas/ravb_main.c > >> [...] > >>> @@ -2290,7 +2308,38 @@ static void ravb_set_rx_csum(struct > >>> net_device *ndev, bool enable) static int > >>> ravb_set_features_rgeth(struct > >> net_device *ndev, > >>> netdev_features_t features) > >>> { > >>> - /* Place holder */ > >>> + netdev_features_t changed = features ^ ndev->features; > >>> + unsigned int reg; > >> > >> u32 reg; > >> > >>> + int error; > >>> + > >>> + reg = ravb_read(ndev, CSR0); > >> > >> ... as this function returns u32. > > I'm even suggesting to call this variable 'csr0'. OK. Will change to u32 csr0. > > [...] > > > Regards, > > Biju > > MBR, Sergey
diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index d42e8ea981df..2275f27c0672 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -209,6 +209,8 @@ enum ravb_reg { CXR56 = 0x0770, /* Documented for RZ/G2L only */ MAFCR = 0x0778, CSR0 = 0x0800, /* Documented for RZ/G2L only */ + CSR1 = 0x0804, /* Documented for RZ/G2L only */ + CSR2 = 0x0808, /* Documented for RZ/G2L only */ }; @@ -978,6 +980,36 @@ enum CSR0_BIT { CSR0_RPE = 0x00000020, }; +enum CSR1_BIT { + CSR1_TIP4 = 0x00000001, + CSR1_TTCP4 = 0x00000010, + CSR1_TUDP4 = 0x00000020, + CSR1_TICMP4 = 0x00000040, + CSR1_TTCP6 = 0x00100000, + CSR1_TUDP6 = 0x00200000, + CSR1_TICMP6 = 0x00400000, + CSR1_THOP = 0x01000000, + CSR1_TROUT = 0x02000000, + CSR1_TAHD = 0x04000000, + CSR1_TDHD = 0x08000000, + CSR1_ALL = 0x0F700071, +}; + +enum CSR2_BIT { + CSR2_RIP4 = 0x00000001, + CSR2_RTCP4 = 0x00000010, + CSR2_RUDP4 = 0x00000020, + CSR2_RICMP4 = 0x00000040, + CSR2_RTCP6 = 0x00100000, + CSR2_RUDP6 = 0x00200000, + CSR2_RICMP6 = 0x00400000, + CSR2_RHOP = 0x01000000, + CSR2_RROUT = 0x02000000, + CSR2_RAHD = 0x04000000, + CSR2_RDHD = 0x08000000, + CSR2_ALL = 0x0F700071, +}; + #define DBAT_ENTRY_NUM 22 #define RX_QUEUE_OFFSET 4 #define NUM_RX_QUEUE 2 diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 72aea5875bc5..641ae5553b64 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1506,6 +1506,24 @@ static void ravb_set_msglevel(struct net_device *ndev, u32 value) priv->msg_enable = value; } +static const char ravb_gstrings_stats_rgeth[][ETH_GSTRING_LEN] = { + "rx_queue_0_current", + "tx_queue_0_current", + "rx_queue_0_dirty", + "tx_queue_0_dirty", + "rx_queue_0_packets", + "tx_queue_0_packets", + "rx_queue_0_bytes", + "tx_queue_0_bytes", + "rx_queue_0_mcast_packets", + "rx_queue_0_errors", + "rx_queue_0_crc_errors", + "rx_queue_0_frame_errors", + "rx_queue_0_length_errors", + "rx_queue_0_csum_offload_errors", + "rx_queue_0_over_errors", +}; + static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { "rx_queue_0_current", "tx_queue_0_current", @@ -2290,7 +2308,38 @@ static void ravb_set_rx_csum(struct net_device *ndev, bool enable) static int ravb_set_features_rgeth(struct net_device *ndev, netdev_features_t features) { - /* Place holder */ + netdev_features_t changed = features ^ ndev->features; + unsigned int reg; + int error; + + reg = ravb_read(ndev, CSR0); + + ravb_write(ndev, reg & ~(CSR0_RPE | CSR0_TPE), CSR0); + error = ravb_wait(ndev, CSR0, CSR0_RPE | CSR0_TPE, 0); + if (error) { + ravb_write(ndev, reg, CSR0); + return error; + } + + if (changed & NETIF_F_RXCSUM) { + if (features & NETIF_F_RXCSUM) + ravb_write(ndev, CSR2_ALL, CSR2); + else + ravb_write(ndev, 0, CSR2); + } + + if (changed & NETIF_F_HW_CSUM) { + if (features & NETIF_F_HW_CSUM) { + ravb_write(ndev, CSR1_ALL, CSR1); + ndev->features |= NETIF_F_CSUM_MASK; + } else { + ravb_write(ndev, 0, CSR1); + } + } + ravb_write(ndev, reg, CSR0); + + ndev->features = features; + return 0; } @@ -2432,6 +2481,11 @@ static const struct ravb_hw_info rgeth_hw_info = { .set_feature = ravb_set_features_rgeth, .dmac_init = ravb_dmac_init_rgeth, .emac_init = ravb_emac_init_rgeth, + .net_hw_features = (NETIF_F_HW_CSUM | NETIF_F_RXCSUM), + .gstrings_stats = ravb_gstrings_stats_rgeth, + .gstrings_size = sizeof(ravb_gstrings_stats_rgeth), + .stats_len = ARRAY_SIZE(ravb_gstrings_stats_rgeth), + .max_rx_len = RGETH_RX_BUFF_MAX + RAVB_ALIGN - 1, .aligned_tx = 1, .tx_counters = 1, .no_gptp = 1,
This patch adds set_feature support for RZ/G2L. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/net/ethernet/renesas/ravb.h | 32 ++++++++++++++ drivers/net/ethernet/renesas/ravb_main.c | 56 +++++++++++++++++++++++- 2 files changed, 87 insertions(+), 1 deletion(-)