| Message ID | 1632478031-12242-3-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | spi: cadence-quadspi: Add Xilinx Versal OSPI support | expand |
On Fri, 24 Sep 2021 15:37:09 +0530, Sai Krishna Potthuri wrote: > Add new compatible to support Cadence Octal SPI(OSPI) controller on > Xilinx Versal SoCs, also add power-domains property to the properties > list and marked as required for Xilinx Versal OSPI compatible. > > Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> > --- > .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/patch/1532183 spi@ff705000: resets: [[6, 37]] is too short arch/arm/boot/dts/socfpga_arria5_socdk.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_socdk.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_sockit.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_socrates.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_sodia.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dt.yaml arch/arm/boot/dts/socfpga_vt.dt.yaml
On Fri, 24 Sep 2021 15:37:09 +0530, Sai Krishna Potthuri wrote: > Add new compatible to support Cadence Octal SPI(OSPI) controller on > Xilinx Versal SoCs, also add power-domains property to the properties > list and marked as required for Xilinx Versal OSPI compatible. > > Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> > --- > .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 0e7087cc8bf9..ca155abbda7a 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -11,6 +11,14 @@ maintainers: allOf: - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + const: xlnx,versal-ospi-1.0 + then: + required: + - power-domains properties: compatible: @@ -20,6 +28,7 @@ properties: - ti,k2g-qspi - ti,am654-ospi - intel,lgm-qspi + - xlnx,versal-ospi-1.0 - const: cdns,qspi-nor - const: cdns,qspi-nor @@ -65,6 +74,9 @@ properties: data rather than the QSPI clock. Make sure that QSPI return clock is populated on the board before using this property. + power-domains: + maxItems: 1 + resets: maxItems: 2
Add new compatible to support Cadence Octal SPI(OSPI) controller on Xilinx Versal SoCs, also add power-domains property to the properties list and marked as required for Xilinx Versal OSPI compatible. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> --- .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)