diff mbox series

[05/10] ravb: Initialize GbEthernet DMAC

Message ID 20211001150636.7500-6-biju.das.jz@bp.renesas.com (mailing list archive)
State Accepted
Commit 660e3d95e21a929d8a718dcbefe5a63bc4418412
Delegated to: Netdev Maintainers
Headers show
Series Add Gigabit Ethernet driver support | expand

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Commit Message

Biju Das Oct. 1, 2021, 3:06 p.m. UTC 
Initialize GbEthernet DMAC found on RZ/G2L SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
RFC->v1:
 * Removed RIC3 initialization from DMAC init, as it is 
   same as reset value.
 * moved stubs function to earlier patches.
 * renamed "rgeth" with "gbeth"
---
 drivers/net/ethernet/renesas/ravb.h      |  3 ++-
 drivers/net/ethernet/renesas/ravb_main.c | 30 +++++++++++++++++++++++-
 2 files changed, 31 insertions(+), 2 deletions(-)

Comments

Sergey Shtylyov Oct. 4, 2021, 12:40 p.m. UTC | #1 
Hello!

On 10/1/21 6:06 PM, Biju Das wrote:

> Initialize GbEthernet DMAC found on RZ/G2L SoC.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> RFC->v1:
>  * Removed RIC3 initialization from DMAC init, as it is 
>    same as reset value.

   I'm not sure we do a reset everytime...

>  * moved stubs function to earlier patches.
>  * renamed "rgeth" with "gbeth"
> ---
>  drivers/net/ethernet/renesas/ravb.h      |  3 ++-
>  drivers/net/ethernet/renesas/ravb_main.c | 30 +++++++++++++++++++++++-
>  2 files changed, 31 insertions(+), 2 deletions(-)
> 
[...]
> diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
> index dc817b4d95a1..5790a9332e7b 100644
> --- a/drivers/net/ethernet/renesas/ravb_main.c
> +++ b/drivers/net/ethernet/renesas/ravb_main.c
> @@ -489,7 +489,35 @@ static void ravb_emac_init(struct net_device *ndev)
>  
>  static int ravb_dmac_init_gbeth(struct net_device *ndev)
>  {
> -	/* Place holder */
> +	int error;
> +
> +	error = ravb_ring_init(ndev, RAVB_BE);
> +	if (error)
> +		return error;
> +
> +	/* Descriptor format */
> +	ravb_ring_format(ndev, RAVB_BE);
> +
> +	/* Set AVB RX */

   AVB? We don't have it, do we?

> +	ravb_write(ndev, 0x60000000, RCR);

   Not even RCR.EFFS? And what do bits 29..30 mean?

[...]
> +	/* Set FIFO size */
> +	ravb_write(ndev, 0x00222200, TGC);

   Do TBD<n> (other than TBD0) fields even exist?

[...]

MBR, Sergey
Biju Das Oct. 4, 2021, 1:12 p.m. UTC | #2 
Hi Sergey,
Thanks for the comments

> Subject: Re: [PATCH 05/10] ravb: Initialize GbEthernet DMAC
> 
> Hello!
> 
> On 10/1/21 6:06 PM, Biju Das wrote:
> 
> > Initialize GbEthernet DMAC found on RZ/G2L SoC.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > RFC->v1:
> >  * Removed RIC3 initialization from DMAC init, as it is
> >    same as reset value.
> 
>    I'm not sure we do a reset everytime...
> 
> >  * moved stubs function to earlier patches.
> >  * renamed "rgeth" with "gbeth"
> > ---
> >  drivers/net/ethernet/renesas/ravb.h      |  3 ++-
> >  drivers/net/ethernet/renesas/ravb_main.c | 30
> > +++++++++++++++++++++++-
> >  2 files changed, 31 insertions(+), 2 deletions(-)
> >
> [...]
> > diff --git a/drivers/net/ethernet/renesas/ravb_main.c
> > b/drivers/net/ethernet/renesas/ravb_main.c
> > index dc817b4d95a1..5790a9332e7b 100644
> > --- a/drivers/net/ethernet/renesas/ravb_main.c
> > +++ b/drivers/net/ethernet/renesas/ravb_main.c
> > @@ -489,7 +489,35 @@ static void ravb_emac_init(struct net_device
> > *ndev)
> >
> >  static int ravb_dmac_init_gbeth(struct net_device *ndev)  {
> > -	/* Place holder */
> > +	int error;
> > +
> > +	error = ravb_ring_init(ndev, RAVB_BE);
> > +	if (error)
> > +		return error;
> > +
> > +	/* Descriptor format */
> > +	ravb_ring_format(ndev, RAVB_BE);
> > +
> > +	/* Set AVB RX */
> 
>    AVB? We don't have it, do we?

Good catch. I Will update the comment in next RFC patch.

> 
> > +	ravb_write(ndev, 0x60000000, RCR);
> 
>    Not even RCR.EFFS? And what do bits 29..30 mean?

RZ/G2L Bit 31 is reserved.
Bit 16:30 Reception fifo critical level.
Bit 15:1 reserved
Bit 0 : EFFS

I am not sure, where do you get 29..30? can you please clarify.


> 
> [...]
> > +	/* Set FIFO size */
> > +	ravb_write(ndev, 0x00222200, TGC);
> 
>    Do TBD<n> (other than TBD0) fields even exist?

Only TBD (Bit 8..9) is available to write, rest all are reserved with remaining values
as in "0x00222200"

Regds,
Biju


> 
> [...]
> 
> MBR, Sergey
Sergey Shtylyov Oct. 4, 2021, 3:50 p.m. UTC | #3 
On 10/4/21 4:12 PM, Biju Das wrote:

>> Subject: Re: [PATCH 05/10] ravb: Initialize GbEthernet DMAC
>>
>> Hello!
>>
>> On 10/1/21 6:06 PM, Biju Das wrote:
>>
>>> Initialize GbEthernet DMAC found on RZ/G2L SoC.
>>>
>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>>> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> ---
>>> RFC->v1:
>>>  * Removed RIC3 initialization from DMAC init, as it is
>>>    same as reset value.
>>
>>    I'm not sure we do a reset everytime...
>>
>>>  * moved stubs function to earlier patches.
>>>  * renamed "rgeth" with "gbeth"
>>> ---
>>>  drivers/net/ethernet/renesas/ravb.h      |  3 ++-
>>>  drivers/net/ethernet/renesas/ravb_main.c | 30
>>> +++++++++++++++++++++++-
>>>  2 files changed, 31 insertions(+), 2 deletions(-)
>>>
>> [...]
>>> diff --git a/drivers/net/ethernet/renesas/ravb_main.c
>>> b/drivers/net/ethernet/renesas/ravb_main.c
>>> index dc817b4d95a1..5790a9332e7b 100644
>>> --- a/drivers/net/ethernet/renesas/ravb_main.c
>>> +++ b/drivers/net/ethernet/renesas/ravb_main.c
>>> @@ -489,7 +489,35 @@ static void ravb_emac_init(struct net_device
>>> *ndev)
>>>
>>>  static int ravb_dmac_init_gbeth(struct net_device *ndev)  {
>>> -	/* Place holder */
>>> +	int error;
>>> +
>>> +	error = ravb_ring_init(ndev, RAVB_BE);
>>> +	if (error)
>>> +		return error;
>>> +
>>> +	/* Descriptor format */
>>> +	ravb_ring_format(ndev, RAVB_BE);
>>> +
>>> +	/* Set AVB RX */
>>
>>    AVB? We don't have it, do we?
> 
> Good catch. I Will update the comment in next RFC patch.

   That's trifles, not worth a patch on its own...

>>
>>> +	ravb_write(ndev, 0x60000000, RCR);
>>
>>    Not even RCR.EFFS? And what do bits 29..30 mean?
> 
> RZ/G2L Bit 31 is reserved.
> Bit 16:30 Reception fifo critical level.
> Bit 15:1 reserved
> Bit 0 : EFFS
> 
> I am not sure, where do you get 29..30? can you please clarify.

   0x60000000 has bits 29..30 set and gen3 manual has these bits reserved. 

>> [...]
>>> +	/* Set FIFO size */
>>> +	ravb_write(ndev, 0x00222200, TGC);
>>
>>    Do TBD<n> (other than TBD0) fields even exist?
> 
> Only TBD (Bit 8..9) is available to write,

   Thought so! :-)

> rest all are reserved with remaining values
> as in "0x00222200"

  Oh, so the defaluts are the sme on RZ/G2L, despite only 1 TX queue?

> Regds,
> Biju

MBR, Sergey
Biju Das Oct. 4, 2021, 6:42 p.m. UTC | #4 
> -----Original Message-----
> From: Sergei Shtylyov <sergei.shtylyov@gmail.com>
> Sent: 04 October 2021 16:51
> To: Biju Das <biju.das.jz@bp.renesas.com>; Sergey Shtylyov
> <s.shtylyov@omp.ru>; David S. Miller <davem@davemloft.net>; Jakub Kicinski
> <kuba@kernel.org>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Sergey Shtylyov
> <s.shtylyov@omprussia.ru>; Adam Ford <aford173@gmail.com>; Andrew Lunn
> <andrew@lunn.ch>; Yuusuke Ashizuka <ashiduka@fujitsu.com>; Yoshihiro
> Shimoda <yoshihiro.shimoda.uh@renesas.com>; netdev@vger.kernel.org; linux-
> renesas-soc@vger.kernel.org; Chris Paterson <Chris.Paterson2@renesas.com>;
> Biju Das <biju.das@bp.renesas.com>; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: Re: [PATCH 05/10] ravb: Initialize GbEthernet DMAC
> 
> On 10/4/21 4:12 PM, Biju Das wrote:
> 
> >> Subject: Re: [PATCH 05/10] ravb: Initialize GbEthernet DMAC
> >>
> >> Hello!
> >>
> >> On 10/1/21 6:06 PM, Biju Das wrote:
> >>
> >>> Initialize GbEthernet DMAC found on RZ/G2L SoC.
> >>>
> >>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> >>> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>> ---
> >>> RFC->v1:
> >>>  * Removed RIC3 initialization from DMAC init, as it is
> >>>    same as reset value.
> >>
> >>    I'm not sure we do a reset everytime...
> >>
> >>>  * moved stubs function to earlier patches.
> >>>  * renamed "rgeth" with "gbeth"
> >>> ---
> >>>  drivers/net/ethernet/renesas/ravb.h      |  3 ++-
> >>>  drivers/net/ethernet/renesas/ravb_main.c | 30
> >>> +++++++++++++++++++++++-
> >>>  2 files changed, 31 insertions(+), 2 deletions(-)
> >>>
> >> [...]
> >>> diff --git a/drivers/net/ethernet/renesas/ravb_main.c
> >>> b/drivers/net/ethernet/renesas/ravb_main.c
> >>> index dc817b4d95a1..5790a9332e7b 100644
> >>> --- a/drivers/net/ethernet/renesas/ravb_main.c
> >>> +++ b/drivers/net/ethernet/renesas/ravb_main.c
> >>> @@ -489,7 +489,35 @@ static void ravb_emac_init(struct net_device
> >>> *ndev)
> >>>
> >>>  static int ravb_dmac_init_gbeth(struct net_device *ndev)  {
> >>> -	/* Place holder */
> >>> +	int error;
> >>> +
> >>> +	error = ravb_ring_init(ndev, RAVB_BE);
> >>> +	if (error)
> >>> +		return error;
> >>> +
> >>> +	/* Descriptor format */
> >>> +	ravb_ring_format(ndev, RAVB_BE);
> >>> +
> >>> +	/* Set AVB RX */
> >>
> >>    AVB? We don't have it, do we?
> >
> > Good catch. I Will update the comment in next RFC patch.
> 
>    That's trifles, not worth a patch on its own...
> 
> >>
> >>> +	ravb_write(ndev, 0x60000000, RCR);
> >>
> >>    Not even RCR.EFFS? And what do bits 29..30 mean?
> >
> > RZ/G2L Bit 31 is reserved.
> > Bit 16:30 Reception fifo critical level.
> > Bit 15:1 reserved
> > Bit 0 : EFFS
> >
> > I am not sure, where do you get 29..30? can you please clarify.
> 
>    0x60000000 has bits 29..30 set and gen3 manual has these bits reserved.
OK.

> 
> >> [...]
> >>> +	/* Set FIFO size */
> >>> +	ravb_write(ndev, 0x00222200, TGC);
> >>
> >>    Do TBD<n> (other than TBD0) fields even exist?
> >
> > Only TBD (Bit 8..9) is available to write,
> 
>    Thought so! :-)
> 
> > rest all are reserved with remaining values as in "0x00222200"
> 
>   Oh, so the defaluts are the sme on RZ/G2L, despite only 1 TX queue?

Yep.

> 
> > Regds,
> > Biju
> 
> MBR, Sergey
diff mbox series

Patch

diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
index f6398fdcead2..9cd3a15743b4 100644
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -81,6 +81,7 @@  enum ravb_reg {
 	RQC3	= 0x00A0,
 	RQC4	= 0x00A4,
 	RPC	= 0x00B0,
+	RTC	= 0x00B4,	/* R-Car Gen3 and RZ/G2L only */
 	UFCW	= 0x00BC,
 	UFCS	= 0x00C0,
 	UFCV0	= 0x00C4,
@@ -193,7 +194,7 @@  enum ravb_reg {
 	GECMR	= 0x05b0,
 	MAHR	= 0x05c0,
 	MALR	= 0x05c8,
-	TROCR	= 0x0700,	/* R-Car Gen3 only */
+	TROCR	= 0x0700,	/* R-Car Gen3 and RZ/G2L only */
 	CEFCR	= 0x0740,
 	FRECR	= 0x0748,
 	TSFRCR	= 0x0750,
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index dc817b4d95a1..5790a9332e7b 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -489,7 +489,35 @@  static void ravb_emac_init(struct net_device *ndev)
 
 static int ravb_dmac_init_gbeth(struct net_device *ndev)
 {
-	/* Place holder */
+	int error;
+
+	error = ravb_ring_init(ndev, RAVB_BE);
+	if (error)
+		return error;
+
+	/* Descriptor format */
+	ravb_ring_format(ndev, RAVB_BE);
+
+	/* Set AVB RX */
+	ravb_write(ndev, 0x60000000, RCR);
+
+	/* Set Max Frame Length (RTC) */
+	ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC);
+
+	/* Set FIFO size */
+	ravb_write(ndev, 0x00222200, TGC);
+
+	ravb_write(ndev, 0, TCCR);
+
+	/* Frame receive */
+	ravb_write(ndev, RIC0_FRE0, RIC0);
+	/* Disable FIFO full warning */
+	ravb_write(ndev, 0x0, RIC1);
+	/* Receive FIFO full error, descriptor empty */
+	ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2);
+
+	ravb_write(ndev, TIC_FTE0, TIC);
+
 	return 0;
 }