| Message ID | 1633376488-545-4-git-send-email-pmaliset@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add DT bindings and DT nodes for PCIe and PHY in SC7280 | expand |
Quoting Prasad Malisetty (2021-10-04 12:41:26) > Enable PCIe controller and PHY for sc7280 IDP board. > Add specific NVMe GPIO entries for SKU1 and SKU2 support. > > Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 8 +++++ > arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 51 ++++++++++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 8 +++++ > 3 files changed, 67 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi > index 272d5ca..b416f3d 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi > @@ -462,6 +491,28 @@ > }; > > &tlmm { > + nvme_pwren_pin: nvme-pwren-pin { pin is sort of redundant but OK. It would be simpler without the pin postfix. > + function = "gpio"; > + bias-pull-up; Why is there a bias pull up on this enable pin? I'd expect to see a bias-disable as this is an output pin and there's no need for a pull. > + }; > + > + pcie1_reset_n: pcie1-reset-n { > + pins = "gpio2"; > + function = "gpio"; > + > + drive-strength = <16>; Why such a strong drive strength? > + output-low; > + bias-disable; > + }; > + > + pcie1_wake_n: pcie1-wake-n { > + pins = "gpio3"; > + function = "gpio"; > + > + drive-strength = <2>; > + bias-pull-up; > + }; > + > qup_uart7_sleep_cts: qup-uart7-sleep-cts { > pins = "gpio28"; > function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 64fc22a..5b1c96b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -61,6 +61,14 @@ modem-init; }; +&nvme_pwren_pin { + pins = "gpio19"; +}; + +&nvme_3v3_regulator { + gpio = <&tlmm 19 GPIO_ACTIVE_HIGH>; +}; + &pmk8350_vadc { pmr735a_die_temp { reg = <PMR735A_ADC7_DIE_TEMP>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 272d5ca..b416f3d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -31,6 +31,18 @@ linux,can-disable; }; }; + + nvme_3v3_regulator: nvme-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "VLDO_3V3"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&nvme_pwren_pin>; + }; }; /* @@ -272,6 +284,23 @@ modem-init; }; +&pcie1 { + status = "okay"; + perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&nvme_3v3_regulator>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>, <&pcie1_reset_n>, <&pcie1_wake_n>; +}; + +&pcie1_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l10c_0p8>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + &pmk8350_vadc { pmk8350_die_temp { reg = <PMK8350_ADC7_DIE_TEMP>; @@ -462,6 +491,28 @@ }; &tlmm { + nvme_pwren_pin: nvme-pwren-pin { + function = "gpio"; + bias-pull-up; + }; + + pcie1_reset_n: pcie1-reset-n { + pins = "gpio2"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-disable; + }; + + pcie1_wake_n: pcie1-wake-n { + pins = "gpio3"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + qup_uart7_sleep_cts: qup-uart7-sleep-cts { pins = "gpio28"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts index 1fc2add..f2722c0 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts @@ -21,3 +21,11 @@ stdout-path = "serial0:115200n8"; }; }; + +&nvme_pwren_pin { + pins = "gpio51"; +}; + +&nvme_3v3_regulator { + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; +};
Enable PCIe controller and PHY for sc7280 IDP board. Add specific NVMe GPIO entries for SKU1 and SKU2 support. Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 8 +++++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 51 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 8 +++++ 3 files changed, 67 insertions(+)