diff mbox series

[v10,5/5] arm64: dts: qcom: sc7280: Enable SoC sleep stats

Message ID 1633425065-7927-6-git-send-email-mkshah@codeaurora.org (mailing list archive)
State Superseded
Headers show
Series Introduce SoC sleep stats driver | expand

Commit Message

Maulik Shah Oct. 5, 2021, 9:11 a.m. UTC
Add device node for SoC sleep stats driver which provides various
low power mode stats.

Also update the reg size of aoss_qmp device to 0x400.

Cc: devicetree@vger.kernel.org
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

Comments

Bjorn Andersson Oct. 5, 2021, 4:09 p.m. UTC | #1
On Tue 05 Oct 02:11 PDT 2021, Maulik Shah wrote:

> Add device node for SoC sleep stats driver which provides various
> low power mode stats.
> 
> Also update the reg size of aoss_qmp device to 0x400.
> 
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>

Can you please follow up with patches for the other upstream platforms
as well.

Thanks,
Bjorn

> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 39635da..f8622ae 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2637,7 +2637,7 @@
>  
>  		aoss_qmp: power-controller@c300000 {
>  			compatible = "qcom,sc7280-aoss-qmp";
> -			reg = <0 0x0c300000 0 0x100000>;
> +			reg = <0 0x0c300000 0 0x400>;
>  			interrupts-extended = <&ipcc IPCC_CLIENT_AOP
>  						     IPCC_MPROC_SIGNAL_GLINK_QMP
>  						     IRQ_TYPE_EDGE_RISING>;
> @@ -2647,6 +2647,11 @@
>  			#clock-cells = <0>;
>  		};
>  
> +		memory@c3f0000 {
> +			compatible = "qcom,rpmh-sleep-stats";
> +			reg = <0 0x0c3f0000 0 0x400>;
> +		};
> +
>  		spmi_bus: spmi@c440000 {
>  			compatible = "qcom,spmi-pmic-arb";
>  			reg = <0 0x0c440000 0 0x1100>,
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
Maulik Shah Oct. 6, 2021, 3:20 p.m. UTC | #2
Hi,

On 10/5/2021 9:39 PM, Bjorn Andersson wrote:
> On Tue 05 Oct 02:11 PDT 2021, Maulik Shah wrote:
> 
>> Add device node for SoC sleep stats driver which provides various
>> low power mode stats.
>>
>> Also update the reg size of aoss_qmp device to 0x400.
>>
>> Cc: devicetree@vger.kernel.org
>> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
> 
> Can you please follow up with patches for the other upstream platforms
> as well.
> 
> Thanks,
> Bjorn
> 

Sure, included most of other upstream platforms in v11.

Thanks,
Maulik

>> ---
>>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 ++++++-
>>   1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 39635da..f8622ae 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -2637,7 +2637,7 @@
>>   
>>   		aoss_qmp: power-controller@c300000 {
>>   			compatible = "qcom,sc7280-aoss-qmp";
>> -			reg = <0 0x0c300000 0 0x100000>;
>> +			reg = <0 0x0c300000 0 0x400>;
>>   			interrupts-extended = <&ipcc IPCC_CLIENT_AOP
>>   						     IPCC_MPROC_SIGNAL_GLINK_QMP
>>   						     IRQ_TYPE_EDGE_RISING>;
>> @@ -2647,6 +2647,11 @@
>>   			#clock-cells = <0>;
>>   		};
>>   
>> +		memory@c3f0000 {
>> +			compatible = "qcom,rpmh-sleep-stats";
>> +			reg = <0 0x0c3f0000 0 0x400>;
>> +		};
>> +
>>   		spmi_bus: spmi@c440000 {
>>   			compatible = "qcom,spmi-pmic-arb";
>>   			reg = <0 0x0c440000 0 0x1100>,
>> -- 
>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
>> of Code Aurora Forum, hosted by The Linux Foundation
>>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 39635da..f8622ae 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2637,7 +2637,7 @@ 
 
 		aoss_qmp: power-controller@c300000 {
 			compatible = "qcom,sc7280-aoss-qmp";
-			reg = <0 0x0c300000 0 0x100000>;
+			reg = <0 0x0c300000 0 0x400>;
 			interrupts-extended = <&ipcc IPCC_CLIENT_AOP
 						     IPCC_MPROC_SIGNAL_GLINK_QMP
 						     IRQ_TYPE_EDGE_RISING>;
@@ -2647,6 +2647,11 @@ 
 			#clock-cells = <0>;
 		};
 
+		memory@c3f0000 {
+			compatible = "qcom,rpmh-sleep-stats";
+			reg = <0 0x0c3f0000 0 0x400>;
+		};
+
 		spmi_bus: spmi@c440000 {
 			compatible = "qcom,spmi-pmic-arb";
 			reg = <0 0x0c440000 0 0x1100>,