| Message ID | 20211006223603.18858-11-ansuelsmth@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | Multiple improvement for qca8337 switch | expand |
| Context | Check | Description |
|---|---|---|
| netdev/cover_letter | success | Series has a cover letter |
| netdev/fixes_present | success | Fixes tag not required for -next series |
| netdev/patch_count | success | Link |
| netdev/tree_selection | success | Clearly marked for net-next |
| netdev/subject_prefix | success | Link |
| netdev/cc_maintainers | success | CCed 8 of 8 maintainers |
| netdev/source_inline | success | Was 0 now: 0 |
| netdev/verify_signedoff | success | Signed-off-by tag matches author and committer |
| netdev/module_param | success | Was 0 now: 0 |
| netdev/build_32bit | success | Errors and warnings before: 0 this patch: 0 |
| netdev/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| netdev/verify_fixes | success | No Fixes tag |
| netdev/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 28 lines checked |
| netdev/build_allmodconfig_warn | success | Errors and warnings before: 0 this patch: 0 |
| netdev/header_inline | success | No static functions without inline keyword in header files |
On Thu, Oct 07, 2021 at 12:36:00AM +0200, Ansuel Smith wrote: > Support enabling PLL on the SGMII CPU port. Some device require this > special configuration or no traffic is transmitted and the switch > doesn't work at all. A dedicated binding is added to the CPU node > port to apply the correct reg on mac config. Why not just enable this all the time when the CPU port is in SGMII mode? Is it also needed for 1000BaseX? DT properties like this are hard to use. It would be better if the switch can decide for itself if it needs the PLL enabled. Andrew
On Thu, Oct 07, 2021 at 02:29:46AM +0200, Andrew Lunn wrote: > On Thu, Oct 07, 2021 at 12:36:00AM +0200, Ansuel Smith wrote: > > Support enabling PLL on the SGMII CPU port. Some device require this > > special configuration or no traffic is transmitted and the switch > > doesn't work at all. A dedicated binding is added to the CPU node > > port to apply the correct reg on mac config. > > Why not just enable this all the time when the CPU port is in SGMII > mode? I don't know if you missed the cover letter with the reason. Sgmii PLL is a mess. Some device needs it and some doesn't. With a wrong configuration the result is not traffic. As it's all messy we decided to set the PLL to be enabled with a dedicated binding and set it disabled by default. We enouncer more device that require it disabled than device that needs it enabled. (in the order of 70 that doesn't needed it and 2 that requires it enabled or port instability/no traffic/leds problem) > > Is it also needed for 1000BaseX? > We assume it really depends on the device. > DT properties like this are hard to use. It would be better if the > switch can decide for itself if it needs the PLL enabled. > Again reason in the cover letter sgmii part. Some qca driver have some logic based on switch revision. We tried that and it didn't work since some device had no traffic with pll enabled (and with the revision set to enable pll) > Andrew
On Thu, Oct 07, 2021 at 03:35:54PM +0200, Ansuel Smith wrote: > On Thu, Oct 07, 2021 at 02:29:46AM +0200, Andrew Lunn wrote: > > On Thu, Oct 07, 2021 at 12:36:00AM +0200, Ansuel Smith wrote: > > > Support enabling PLL on the SGMII CPU port. Some device require this > > > special configuration or no traffic is transmitted and the switch > > > doesn't work at all. A dedicated binding is added to the CPU node > > > port to apply the correct reg on mac config. > > > > Why not just enable this all the time when the CPU port is in SGMII > > mode? > > I don't know if you missed the cover letter with the reason. Sgmii PLL > is a mess. Some device needs it and some doesn't. With a wrong > configuration the result is not traffic. As it's all messy we decided to > set the PLL to be enabled with a dedicated binding and set it disabled > by default. We enouncer more device that require it disabled than device > that needs it enabled. (in the order of 70 that doesn't needed it and 2 > that requires it enabled or port instability/no traffic/leds problem) What exactly does this PLL do? Clock recovery of the SGMII clock, and then using it in the opposite direction? What combinations of PHYs need it, and which don't? > > Is it also needed for 1000BaseX? > > > > We assume it really depends on the device. That i find surprising. 1000BaseX and SGMII are very similar. I would expect a device with requires the PLL enabled for SGMII also needs it for 1000BaseX. > > DT properties like this are hard to use. It would be better if the > > switch can decide for itself if it needs the PLL enabled. > > Again reason in the cover letter sgmii part. Some qca driver have some > logic based on switch revision. We tried that and it didn't work since > some device had no traffic with pll enabled (and with the revision set > to enable pll) This is my main problem with this patchset. You are adding lots of poorly documented properties which are proprietary to this switch. And you are saying, please try all 2^N combinations and see what works best. That is not very friendly at all. So it would be good to explain each one in detail. Maybe given the explanation, we can figure out a way to detect at runtime, and not need the option. If not, you can add it to the DT binding to help somebody pick a likely starting point for the 2^N search. Andrew
On Thu, Oct 07, 2021 at 08:05:56PM +0200, Andrew Lunn wrote: > > On Thu, Oct 07, 2021 at 03:35:54PM +0200, Ansuel Smith wrote: > > On Thu, Oct 07, 2021 at 02:29:46AM +0200, Andrew Lunn wrote: > > > On Thu, Oct 07, 2021 at 12:36:00AM +0200, Ansuel Smith wrote: > > > > Support enabling PLL on the SGMII CPU port. Some device require this > > > > special configuration or no traffic is transmitted and the switch > > > > doesn't work at all. A dedicated binding is added to the CPU node > > > > port to apply the correct reg on mac config. > > > > > > Why not just enable this all the time when the CPU port is in SGMII > > > mode? > > > > I don't know if you missed the cover letter with the reason. Sgmii PLL > > is a mess. Some device needs it and some doesn't. With a wrong > > configuration the result is not traffic. As it's all messy we decided to > > set the PLL to be enabled with a dedicated binding and set it disabled > > by default. We enouncer more device that require it disabled than device > > that needs it enabled. (in the order of 70 that doesn't needed it and 2 > > that requires it enabled or port instability/no traffic/leds problem) > > What exactly does this PLL do? Clock recovery of the SGMII clock, and > then using it in the opposite direction? What combinations of PHYs > need it, and which don't? > I will quote from Documentation bit 1: enable SGMII PLL (it's disabled by default) bit 2: enable rx chain. By default it's disabled and CLK125M_RX and DOUT_RX can be any logic of 1 or 0 bit 3: enable TX driver. By default is in idle and kept in 900mV As you can see normally all these bit are disabled and I think forcing them on seems wrong. We can think about setting it based on the switch type and revision but again we found some that needed it anyway and goes out of any logic. The original idea is to add a biding to force the setting and make the driver decide itself the correct option. But considering we found that in 90% of the case, this is not needed, the switch default doesn't enable it and that only 2-3 device require it, I see the binding the only way to implement this and do not pollute the code with tons of condition. > > > Is it also needed for 1000BaseX? > > > > > > > We assume it really depends on the device. > > That i find surprising. 1000BaseX and SGMII are very similar. I would > expect a device with requires the PLL enabled for SGMII also needs it > for 1000BaseX. > With assume I mean we have no device with 1000BaseX (and I honestly don't know if it does exist) I think if it does require PLL for sgmii then it does require it also for 1000BaseX > > > DT properties like this are hard to use. It would be better if the > > > switch can decide for itself if it needs the PLL enabled. > > > > Again reason in the cover letter sgmii part. Some qca driver have some > > logic based on switch revision. We tried that and it didn't work since > > some device had no traffic with pll enabled (and with the revision set > > to enable pll) > > This is my main problem with this patchset. You are adding lots of > poorly documented properties which are proprietary to this switch. And > you are saying, please try all 2^N combinations and see what works > best. That is not very friendly at all. We have many device and we notice a common config for both qca8327 and qca8337. Wonder if this would be improved by adding some hint in the documentation on the correct configuration based on the switch model? We waited so much to push this just to check if all this bad stuff was actually needed or could be implemented differently, but we really find any logic. So I think the only way is ""spam"" the documentation with data on how to decide the correct option. > > So it would be good to explain each one in detail. Maybe given the > explanation, we can figure out a way to detect at runtime, and not > need the option. If not, you can add it to the DT binding to help > somebody pick a likely starting point for the 2^N search. > > Andrew
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 4d4f23f7f948..01b05dfeae2b 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1214,6 +1214,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, const struct phylink_link_state *state) { struct qca8k_priv *priv = ds->priv; + struct dsa_port *dp; u32 reg, val; int ret; @@ -1282,6 +1283,8 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, break; case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_1000BASEX: + dp = dsa_to_port(ds, port); + /* Enable SGMII on the port */ qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN); @@ -1300,8 +1303,11 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, if (ret) return; - val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | - QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD; + val |= QCA8K_SGMII_EN_SD; + + if (of_property_read_bool(dp->dn, "qca,sgmii-enable-pll")) + val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | + QCA8K_SGMII_EN_TX; if (dsa_is_cpu_port(ds, port)) { /* CPU port, we're talking to the CPU MAC, be a PHY */
Support enabling PLL on the SGMII CPU port. Some device require this special configuration or no traffic is transmitted and the switch doesn't work at all. A dedicated binding is added to the CPU node port to apply the correct reg on mac config. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> --- drivers/net/dsa/qca8k.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)