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[net-next,07/13] net: dsa: qca8k: add support for mac6_exchange, sgmii falling edge

Message ID 20211006223603.18858-8-ansuelsmth@gmail.com (mailing list archive)
State Superseded
Delegated to: Netdev Maintainers
Headers show
Series Multiple improvement for qca8337 switch | expand

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Commit Message

Christian Marangi Oct. 6, 2021, 10:35 p.m. UTC 
Some device set the switch to exchange the mac0 port with mac6 port. Add
support for this in the qca8k driver. Also add support for SGMII rx/tx
clock falling edge. This is only present for pad0, pad5 and pad6 have
these bit reserved from Documentation.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
---
 drivers/net/dsa/qca8k.c | 33 +++++++++++++++++++++++++++++++++
 drivers/net/dsa/qca8k.h |  3 +++
 2 files changed, 36 insertions(+)

Comments

Andrew Lunn Oct. 7, 2021, 12:14 a.m. UTC | #1 
On Thu, Oct 07, 2021 at 12:35:57AM +0200, Ansuel Smith wrote:
> Some device set the switch to exchange the mac0 port with mac6 port. Add
> support for this in the qca8k driver. Also add support for SGMII rx/tx
> clock falling edge. This is only present for pad0, pad5 and pad6 have
> these bit reserved from Documentation.
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>

Who wrote this patch? The person submitting it should be last. If
Matthew actually wrote it, you want to play with git commit --author=
to set the correct author.

   Andrew
Christian Marangi Oct. 7, 2021, 1:26 p.m. UTC | #2 
On Thu, Oct 07, 2021 at 02:14:18AM +0200, Andrew Lunn wrote:
> On Thu, Oct 07, 2021 at 12:35:57AM +0200, Ansuel Smith wrote:
> > Some device set the switch to exchange the mac0 port with mac6 port. Add
> > support for this in the qca8k driver. Also add support for SGMII rx/tx
> > clock falling edge. This is only present for pad0, pad5 and pad6 have
> > these bit reserved from Documentation.
> > 
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
> 
> Who wrote this patch? The person submitting it should be last. If
> Matthew actually wrote it, you want to play with git commit --author=
> to set the correct author.
> 
>    Andrew

I wrote it and Matthew did some very minor changes (binding name).
Should I use co-developed by ?
Andrew Lunn Oct. 7, 2021, 4:49 p.m. UTC | #3 
On Thu, Oct 07, 2021 at 03:26:53PM +0200, Ansuel Smith wrote:
> On Thu, Oct 07, 2021 at 02:14:18AM +0200, Andrew Lunn wrote:
> > On Thu, Oct 07, 2021 at 12:35:57AM +0200, Ansuel Smith wrote:
> > > Some device set the switch to exchange the mac0 port with mac6 port. Add
> > > support for this in the qca8k driver. Also add support for SGMII rx/tx
> > > clock falling edge. This is only present for pad0, pad5 and pad6 have
> > > these bit reserved from Documentation.
> > > 
> > > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > > Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
> > 
> > Who wrote this patch? The person submitting it should be last. If
> > Matthew actually wrote it, you want to play with git commit --author=
> > to set the correct author.
> > 
> >    Andrew
> 
> I wrote it and Matthew did some very minor changes (binding name).
> Should I use co-developed by ?

In that case, just reverse the order of the two Signed-off-by, and
leave the author information as you.

      Andrew
Christian Marangi Oct. 7, 2021, 5:09 p.m. UTC | #4 
On Thu, Oct 07, 2021 at 06:49:06PM +0200, Andrew Lunn wrote:
> On Thu, Oct 07, 2021 at 03:26:53PM +0200, Ansuel Smith wrote:
> > On Thu, Oct 07, 2021 at 02:14:18AM +0200, Andrew Lunn wrote:
> > > On Thu, Oct 07, 2021 at 12:35:57AM +0200, Ansuel Smith wrote:
> > > > Some device set the switch to exchange the mac0 port with mac6 port. Add
> > > > support for this in the qca8k driver. Also add support for SGMII rx/tx
> > > > clock falling edge. This is only present for pad0, pad5 and pad6 have
> > > > these bit reserved from Documentation.
> > > > 
> > > > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > > > Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
> > > 
> > > Who wrote this patch? The person submitting it should be last. If
> > > Matthew actually wrote it, you want to play with git commit --author=
> > > to set the correct author.
> > > 
> > >    Andrew
> > 
> > I wrote it and Matthew did some very minor changes (binding name).
> > Should I use co-developed by ?
> 
> In that case, just reverse the order of the two Signed-off-by, and
> leave the author information as you.
> 
>       Andrew

Ok will fix in v2.
Vladimir Oltean Oct. 10, 2021, 11:40 a.m. UTC | #5 
On Thu, Oct 07, 2021 at 12:35:57AM +0200, Ansuel Smith wrote:
> Some device set the switch to exchange the mac0 port with mac6 port. Add
> support for this in the qca8k driver. Also add support for SGMII rx/tx
> clock falling edge. This is only present for pad0, pad5 and pad6 have
> these bit reserved from Documentation.
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
> ---
>  drivers/net/dsa/qca8k.c | 33 +++++++++++++++++++++++++++++++++
>  drivers/net/dsa/qca8k.h |  3 +++
>  2 files changed, 36 insertions(+)
> 
> diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
> index 5bce7ac4dea7..3a040a3ed58e 100644
> --- a/drivers/net/dsa/qca8k.c
> +++ b/drivers/net/dsa/qca8k.c
> @@ -973,6 +973,34 @@ qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
>  	return ret;
>  }
>  
> +static int
> +qca8k_setup_port0_pad_ctrl_reg(struct qca8k_priv *priv)
> +{
> +	struct device_node *node = priv->dev->of_node;
> +	u32 mask = 0;
> +	int ret = 0;
> +
> +	/* Swap MAC0-MAC6 */
> +	if (of_property_read_bool(node, "qca,mac6-exchange"))
> +		mask |= QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG;
> +
> +	/* SGMII Clock phase configuration */
> +	if (of_property_read_bool(node, "qca,sgmii-rxclk-falling-edge"))
> +		mask |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
> +
> +	if (of_property_read_bool(node, "qca,sgmii-txclk-falling-edge"))
> +		mask |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
> +
> +	if (mask)
> +		ret = qca8k_rmw(priv, QCA8K_REG_PORT0_PAD_CTRL,
> +				QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG |
> +				QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
> +				QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
> +				mask);
> +
> +	return ret;
> +}
> +
>  static int
>  qca8k_setup(struct dsa_switch *ds)
>  {
> @@ -1006,6 +1034,11 @@ qca8k_setup(struct dsa_switch *ds)
>  	if (ret)
>  		return ret;
>  
> +	/* Configure additional PORT0_PAD_CTRL properties */
> +	ret = qca8k_setup_port0_pad_ctrl_reg(priv);
> +	if (ret)
> +		return ret;
> +
>  	/* Enable CPU Port */
>  	ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
>  			    QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
> diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
> index fc7db94cc0c9..3fded69a6839 100644
> --- a/drivers/net/dsa/qca8k.h
> +++ b/drivers/net/dsa/qca8k.h
> @@ -35,6 +35,9 @@
>  #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK		GENMASK(15, 8)
>  #define   QCA8K_MASK_CTRL_DEVICE_ID(x)			((x) >> 8)
>  #define QCA8K_REG_PORT0_PAD_CTRL			0x004
> +#define   QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG		BIT(31)

Where can I find more information about this mac0/mac6 exchange? In this
document for ar8327, bit 31 of PORT0 PAD MODE CTRL is reserved.
http://www.datasheet.es/PDF/771154/AR8327-pdf.html

> +#define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE	BIT(19)
> +#define   QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE	BIT(18)
>  #define QCA8K_REG_PORT5_PAD_CTRL			0x008
>  #define QCA8K_REG_PORT6_PAD_CTRL			0x00c
>  #define   QCA8K_PORT_PAD_RGMII_EN			BIT(26)
> -- 
> 2.32.0
>
Christian Marangi Oct. 10, 2021, noon UTC | #6 
On Sun, Oct 10, 2021 at 02:40:37PM +0300, Vladimir Oltean wrote:
> On Thu, Oct 07, 2021 at 12:35:57AM +0200, Ansuel Smith wrote:
> > Some device set the switch to exchange the mac0 port with mac6 port. Add
> > support for this in the qca8k driver. Also add support for SGMII rx/tx
> > clock falling edge. This is only present for pad0, pad5 and pad6 have
> > these bit reserved from Documentation.
> > 
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
> > ---
> >  drivers/net/dsa/qca8k.c | 33 +++++++++++++++++++++++++++++++++
> >  drivers/net/dsa/qca8k.h |  3 +++
> >  2 files changed, 36 insertions(+)
> > 
> > diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
> > index 5bce7ac4dea7..3a040a3ed58e 100644
> > --- a/drivers/net/dsa/qca8k.c
> > +++ b/drivers/net/dsa/qca8k.c
> > @@ -973,6 +973,34 @@ qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
> >  	return ret;
> >  }
> >  
> > +static int
> > +qca8k_setup_port0_pad_ctrl_reg(struct qca8k_priv *priv)
> > +{
> > +	struct device_node *node = priv->dev->of_node;
> > +	u32 mask = 0;
> > +	int ret = 0;
> > +
> > +	/* Swap MAC0-MAC6 */
> > +	if (of_property_read_bool(node, "qca,mac6-exchange"))
> > +		mask |= QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG;
> > +
> > +	/* SGMII Clock phase configuration */
> > +	if (of_property_read_bool(node, "qca,sgmii-rxclk-falling-edge"))
> > +		mask |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
> > +
> > +	if (of_property_read_bool(node, "qca,sgmii-txclk-falling-edge"))
> > +		mask |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
> > +
> > +	if (mask)
> > +		ret = qca8k_rmw(priv, QCA8K_REG_PORT0_PAD_CTRL,
> > +				QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG |
> > +				QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
> > +				QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
> > +				mask);
> > +
> > +	return ret;
> > +}
> > +
> >  static int
> >  qca8k_setup(struct dsa_switch *ds)
> >  {
> > @@ -1006,6 +1034,11 @@ qca8k_setup(struct dsa_switch *ds)
> >  	if (ret)
> >  		return ret;
> >  
> > +	/* Configure additional PORT0_PAD_CTRL properties */
> > +	ret = qca8k_setup_port0_pad_ctrl_reg(priv);
> > +	if (ret)
> > +		return ret;
> > +
> >  	/* Enable CPU Port */
> >  	ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
> >  			    QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
> > diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
> > index fc7db94cc0c9..3fded69a6839 100644
> > --- a/drivers/net/dsa/qca8k.h
> > +++ b/drivers/net/dsa/qca8k.h
> > @@ -35,6 +35,9 @@
> >  #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK		GENMASK(15, 8)
> >  #define   QCA8K_MASK_CTRL_DEVICE_ID(x)			((x) >> 8)
> >  #define QCA8K_REG_PORT0_PAD_CTRL			0x004
> > +#define   QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG		BIT(31)
> 
> Where can I find more information about this mac0/mac6 exchange? In this
> document for ar8327, bit 31 of PORT0 PAD MODE CTRL is reserved.
> http://www.datasheet.es/PDF/771154/AR8327-pdf.html
>

The documentation for mac06 exchange is in qca8337.
https://github.com/Deoptim/atheros/blob/master/QCA8337-datasheet.pdf
We have this theory that the bit is just reserved in qca8327 due to bad
documentation/qca hiding special stuff. But you could be right and 06
exchange is just not supported on qca8327.
We tought it was like that as many wiki report uncorrect switch in the
devices and by inspecting the real internal photo they were actually
qca8337 instead of qca8327. From initial check it seems that we actually
don't have device with qca8327 and that use mac06 exchange. (We had 8
before and they are all report the wrong switch in the wiki)

> > +#define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE	BIT(19)
> > +#define   QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE	BIT(18)
> >  #define QCA8K_REG_PORT5_PAD_CTRL			0x008
> >  #define QCA8K_REG_PORT6_PAD_CTRL			0x00c
> >  #define   QCA8K_PORT_PAD_RGMII_EN			BIT(26)
> > -- 
> > 2.32.0
> >
diff mbox series

Patch

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 5bce7ac4dea7..3a040a3ed58e 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -973,6 +973,34 @@  qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
 	return ret;
 }
 
+static int
+qca8k_setup_port0_pad_ctrl_reg(struct qca8k_priv *priv)
+{
+	struct device_node *node = priv->dev->of_node;
+	u32 mask = 0;
+	int ret = 0;
+
+	/* Swap MAC0-MAC6 */
+	if (of_property_read_bool(node, "qca,mac6-exchange"))
+		mask |= QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG;
+
+	/* SGMII Clock phase configuration */
+	if (of_property_read_bool(node, "qca,sgmii-rxclk-falling-edge"))
+		mask |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
+
+	if (of_property_read_bool(node, "qca,sgmii-txclk-falling-edge"))
+		mask |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
+
+	if (mask)
+		ret = qca8k_rmw(priv, QCA8K_REG_PORT0_PAD_CTRL,
+				QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG |
+				QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
+				QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
+				mask);
+
+	return ret;
+}
+
 static int
 qca8k_setup(struct dsa_switch *ds)
 {
@@ -1006,6 +1034,11 @@  qca8k_setup(struct dsa_switch *ds)
 	if (ret)
 		return ret;
 
+	/* Configure additional PORT0_PAD_CTRL properties */
+	ret = qca8k_setup_port0_pad_ctrl_reg(priv);
+	if (ret)
+		return ret;
+
 	/* Enable CPU Port */
 	ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
 			    QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index fc7db94cc0c9..3fded69a6839 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -35,6 +35,9 @@ 
 #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK		GENMASK(15, 8)
 #define   QCA8K_MASK_CTRL_DEVICE_ID(x)			((x) >> 8)
 #define QCA8K_REG_PORT0_PAD_CTRL			0x004
+#define   QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG		BIT(31)
+#define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE	BIT(19)
+#define   QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE	BIT(18)
 #define QCA8K_REG_PORT5_PAD_CTRL			0x008
 #define QCA8K_REG_PORT6_PAD_CTRL			0x00c
 #define   QCA8K_PORT_PAD_RGMII_EN			BIT(26)