| Message ID | 20211012163613.30030-14-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 3d6b24a2ada3d53f7da9362d03856bdec74806e5 |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | Add functional support for Gigabit Ethernet driver | expand |
| Context | Check | Description |
|---|---|---|
| netdev/cover_letter | success | Series has a cover letter |
| netdev/fixes_present | success | Fixes tag not required for -next series |
| netdev/patch_count | success | Link |
| netdev/tree_selection | success | Clearly marked for net-next |
| netdev/subject_prefix | success | Link |
| netdev/cc_maintainers | success | CCed 8 of 8 maintainers |
| netdev/source_inline | success | Was 0 now: 0 |
| netdev/verify_signedoff | success | Signed-off-by tag matches author and committer |
| netdev/module_param | success | Was 0 now: 0 |
| netdev/build_32bit | success | Errors and warnings before: 0 this patch: 0 |
| netdev/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| netdev/verify_fixes | success | No Fixes tag |
| netdev/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 37 lines checked |
| netdev/build_allmodconfig_warn | success | Errors and warnings before: 0 this patch: 0 |
| netdev/header_inline | success | No static functions without inline keyword in header files |
On 10/12/21 7:36 PM, Biju Das wrote: > This patch enables Receive/Transmit port of TOE and removes > the setting of promiscuous bit from EMAC configuration mode register. > > This patch also update EMAC configuration mode comment from > "PAUSE prohibition" to "EMAC Mode: PAUSE prohibition; Duplex; TX; > RX; CRC Pass Through". I'm not sure why you set ECMR.RCPT while you don't have the checksum offloaded... > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > v2->v3: > * Enabled TPE/RPE of TOE, as disabling causes loopback test to fail > * Documented CSR0 register bits > * Removed PRM setting from EMAC configuration mode > * Updated EMAC configuration mode. > v1->v2: > * No change > V1: > * New patch. > --- > drivers/net/ethernet/renesas/ravb.h | 6 ++++++ > drivers/net/ethernet/renesas/ravb_main.c | 5 +++-- > 2 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h > index 69a771526776..08062d73df10 100644 > --- a/drivers/net/ethernet/renesas/ravb.h > +++ b/drivers/net/ethernet/renesas/ravb.h > @@ -204,6 +204,7 @@ enum ravb_reg { > TLFRCR = 0x0758, > RFCR = 0x0760, > MAFCR = 0x0778, > + CSR0 = 0x0800, /* RZ/G2L only */ > }; > > > @@ -964,6 +965,11 @@ enum CXR31_BIT { > CXR31_SEL_LINK1 = 0x00000008, > }; > > +enum CSR0_BIT { > + CSR0_TPE = 0x00000010, > + CSR0_RPE = 0x00000020, > +}; > + Is this really needed if you have ECMR.RCPT cleared? [...] MBR, Sergey
Hi Sergey, Thanks for the feedback. > Subject: Re: [PATCH net-next v3 13/14] ravb: Update ravb_emac_init_gbeth() > > On 10/12/21 7:36 PM, Biju Das wrote: > > > This patch enables Receive/Transmit port of TOE and removes the > > setting of promiscuous bit from EMAC configuration mode register. > > > > This patch also update EMAC configuration mode comment from "PAUSE > > prohibition" to "EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC > > Pass Through". > > I'm not sure why you set ECMR.RCPT while you don't have the checksum > offloaded... > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > v2->v3: > > * Enabled TPE/RPE of TOE, as disabling causes loopback test to fail > > * Documented CSR0 register bits > > * Removed PRM setting from EMAC configuration mode > > * Updated EMAC configuration mode. > > v1->v2: > > * No change > > V1: > > * New patch. > > --- > > drivers/net/ethernet/renesas/ravb.h | 6 ++++++ > > drivers/net/ethernet/renesas/ravb_main.c | 5 +++-- > > 2 files changed, 9 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/net/ethernet/renesas/ravb.h > > b/drivers/net/ethernet/renesas/ravb.h > > index 69a771526776..08062d73df10 100644 > > --- a/drivers/net/ethernet/renesas/ravb.h > > +++ b/drivers/net/ethernet/renesas/ravb.h > > @@ -204,6 +204,7 @@ enum ravb_reg { > > TLFRCR = 0x0758, > > RFCR = 0x0760, > > MAFCR = 0x0778, > > + CSR0 = 0x0800, /* RZ/G2L only */ > > }; > > > > > > @@ -964,6 +965,11 @@ enum CXR31_BIT { > > CXR31_SEL_LINK1 = 0x00000008, > > }; > > > > +enum CSR0_BIT { > > + CSR0_TPE = 0x00000010, > > + CSR0_RPE = 0x00000020, > > +}; > > + > > Is this really needed if you have ECMR.RCPT cleared? Yes it is required. Please see the current log and log with the changes you suggested root@smarc-rzg2l:/rzg2l-test-scripts# ./eth_t_001.sh [ 39.646891] ravb 11c20000.ethernet eth0: Link is Down [ 39.715127] ravb 11c30000.ethernet eth1: Link is Down [ 39.895680] Microchip KSZ9131 Gigabit PHY 11c20000.ethernet-ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c20000.ethernet-ffffffff:07, irq=POLL) [ 39.966370] Microchip KSZ9131 Gigabit PHY 11c30000.ethernet-ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c30000.ethernet-ffffffff:07, irq=POLL) [ 42.988573] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready [ 42.995119] ravb 11c20000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off [ 43.052541] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready [ 43.055710] ravb 11c30000.ethernet eth1: Link is Up - 1Gbps/Full - flow control off EXIT|PASS||[422391:43:00] || root@smarc-rzg2l:/rzg2l-test-scripts# with the changes you suggested ---------------------------- root@smarc-rzg2l:/rzg2l-test-scripts# ./eth_t_001.sh [ 23.300520] ravb 11c20000.ethernet eth0: Link is Down [ 23.535604] ravb 11c30000.ethernet eth1: device will be stopped after h/w processes are done. [ 23.547267] ravb 11c30000.ethernet eth1: Link is Down [ 23.802667] Microchip KSZ9131 Gigabit PHY 11c20000.ethernet-ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c20000.ethernet-ffffffff:07, irq=POLL) [ 24.031711] ravb 11c30000.ethernet eth1: failed to switch device to config mode RTNETLINK answers: Connection timed out EXIT|FAIL||[422391:42:32] Failed to bring up ETH1|| root@smarc-rzg2l:/rzg2l-test-scripts# diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index f08d8f2b4d41..b34670a812fd 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -521,7 +521,7 @@ static void ravb_emac_init_gbeth(struct net_device *ndev) /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | - ECMR_TE | ECMR_RE | ECMR_RCPT | + ECMR_TE | ECMR_RE | ECMR_TXF | ECMR_RXF, ECMR); ravb_set_rate_gbeth(ndev); @@ -534,7 +534,7 @@ static void ravb_emac_init_gbeth(struct net_device *ndev) /* E-MAC status register clear */ ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); - ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); + //ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); Regards, Biju > > [...] > > MBR, Sergey
On 10/12/21 8:52 PM, Biju Das wrote: >>> This patch enables Receive/Transmit port of TOE and removes the >>> setting of promiscuous bit from EMAC configuration mode register. >>> >>> This patch also update EMAC configuration mode comment from "PAUSE >>> prohibition" to "EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC >>> Pass Through". >> >> I'm not sure why you set ECMR.RCPT while you don't have the checksum >> offloaded... >> >>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> >>> --- >>> v2->v3: >>> * Enabled TPE/RPE of TOE, as disabling causes loopback test to fail >>> * Documented CSR0 register bits >>> * Removed PRM setting from EMAC configuration mode >>> * Updated EMAC configuration mode. >>> v1->v2: >>> * No change >>> V1: >>> * New patch. >>> --- >>> drivers/net/ethernet/renesas/ravb.h | 6 ++++++ >>> drivers/net/ethernet/renesas/ravb_main.c | 5 +++-- >>> 2 files changed, 9 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/net/ethernet/renesas/ravb.h >>> b/drivers/net/ethernet/renesas/ravb.h >>> index 69a771526776..08062d73df10 100644 >>> --- a/drivers/net/ethernet/renesas/ravb.h >>> +++ b/drivers/net/ethernet/renesas/ravb.h >>> @@ -204,6 +204,7 @@ enum ravb_reg { >>> TLFRCR = 0x0758, >>> RFCR = 0x0760, >>> MAFCR = 0x0778, >>> + CSR0 = 0x0800, /* RZ/G2L only */ >>> }; >>> >>> >>> @@ -964,6 +965,11 @@ enum CXR31_BIT { >>> CXR31_SEL_LINK1 = 0x00000008, >>> }; >>> >>> +enum CSR0_BIT { >>> + CSR0_TPE = 0x00000010, >>> + CSR0_RPE = 0x00000020, >>> +}; >>> + >> >> Is this really needed if you have ECMR.RCPT cleared? > > Yes it is required. Please see the current log and log with the changes you suggested > > root@smarc-rzg2l:/rzg2l-test-scripts# ./eth_t_001.sh > [ 39.646891] ravb 11c20000.ethernet eth0: Link is Down > [ 39.715127] ravb 11c30000.ethernet eth1: Link is Down > [ 39.895680] Microchip KSZ9131 Gigabit PHY 11c20000.ethernet-ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c20000.ethernet-ffffffff:07, irq=POLL) > [ 39.966370] Microchip KSZ9131 Gigabit PHY 11c30000.ethernet-ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c30000.ethernet-ffffffff:07, irq=POLL) > [ 42.988573] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready > [ 42.995119] ravb 11c20000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off > [ 43.052541] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready > [ 43.055710] ravb 11c30000.ethernet eth1: Link is Up - 1Gbps/Full - flow control off > > EXIT|PASS||[422391:43:00] || > > root@smarc-rzg2l:/rzg2l-test-scripts# > > > with the changes you suggested > ---------------------------- > > root@smarc-rzg2l:/rzg2l-test-scripts# ./eth_t_001.sh > [ 23.300520] ravb 11c20000.ethernet eth0: Link is Down > [ 23.535604] ravb 11c30000.ethernet eth1: device will be stopped after h/w processes are done. > [ 23.547267] ravb 11c30000.ethernet eth1: Link is Down > [ 23.802667] Microchip KSZ9131 Gigabit PHY 11c20000.ethernet-ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c20000.ethernet-ffffffff:07, irq=POLL) > [ 24.031711] ravb 11c30000.ethernet eth1: failed to switch device to config mode > RTNETLINK answers: Connection timed out > > EXIT|FAIL||[422391:42:32] Failed to bring up ETH1|| > > root@smarc-rzg2l:/rzg2l-test-scripts# Hm... :-/ What if you only clear ECMR.RCPT but continue to set CSR0? MBR, Sergey
Hi Sergey, > Subject: Re: [PATCH net-next v3 13/14] ravb: Update ravb_emac_init_gbeth() > > On 10/12/21 8:52 PM, Biju Das wrote: > > >>> This patch enables Receive/Transmit port of TOE and removes the > >>> setting of promiscuous bit from EMAC configuration mode register. > >>> > >>> This patch also update EMAC configuration mode comment from "PAUSE > >>> prohibition" to "EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC > >>> Pass Through". > >> > >> I'm not sure why you set ECMR.RCPT while you don't have the > >> checksum offloaded... > >> > >>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > >>> --- > >>> v2->v3: > >>> * Enabled TPE/RPE of TOE, as disabling causes loopback test to fail > >>> * Documented CSR0 register bits > >>> * Removed PRM setting from EMAC configuration mode > >>> * Updated EMAC configuration mode. > >>> v1->v2: > >>> * No change > >>> V1: > >>> * New patch. > >>> --- > >>> drivers/net/ethernet/renesas/ravb.h | 6 ++++++ > >>> drivers/net/ethernet/renesas/ravb_main.c | 5 +++-- > >>> 2 files changed, 9 insertions(+), 2 deletions(-) > >>> > >>> diff --git a/drivers/net/ethernet/renesas/ravb.h > >>> b/drivers/net/ethernet/renesas/ravb.h > >>> index 69a771526776..08062d73df10 100644 > >>> --- a/drivers/net/ethernet/renesas/ravb.h > >>> +++ b/drivers/net/ethernet/renesas/ravb.h > >>> @@ -204,6 +204,7 @@ enum ravb_reg { > >>> TLFRCR = 0x0758, > >>> RFCR = 0x0760, > >>> MAFCR = 0x0778, > >>> + CSR0 = 0x0800, /* RZ/G2L only */ > >>> }; > >>> > >>> > >>> @@ -964,6 +965,11 @@ enum CXR31_BIT { > >>> CXR31_SEL_LINK1 = 0x00000008, > >>> }; > >>> > >>> +enum CSR0_BIT { > >>> + CSR0_TPE = 0x00000010, > >>> + CSR0_RPE = 0x00000020, > >>> +}; > >>> + > >> > >> Is this really needed if you have ECMR.RCPT cleared? > > > > Yes it is required. Please see the current log and log with the > > changes you suggested > > > > root@smarc-rzg2l:/rzg2l-test-scripts# ./eth_t_001.sh > > [ 39.646891] ravb 11c20000.ethernet eth0: Link is Down > > [ 39.715127] ravb 11c30000.ethernet eth1: Link is Down > > [ 39.895680] Microchip KSZ9131 Gigabit PHY 11c20000.ethernet- > ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c20000.ethernet- > ffffffff:07, irq=POLL) > > [ 39.966370] Microchip KSZ9131 Gigabit PHY 11c30000.ethernet- > ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c30000.ethernet- > ffffffff:07, irq=POLL) > > [ 42.988573] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready > > [ 42.995119] ravb 11c20000.ethernet eth0: Link is Up - 1Gbps/Full - > flow control off > > [ 43.052541] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready > > [ 43.055710] ravb 11c30000.ethernet eth1: Link is Up - 1Gbps/Full - > flow control off > > > > EXIT|PASS||[422391:43:00] || > > > > root@smarc-rzg2l:/rzg2l-test-scripts# > > > > > > with the changes you suggested > > ---------------------------- > > > > root@smarc-rzg2l:/rzg2l-test-scripts# ./eth_t_001.sh > > [ 23.300520] ravb 11c20000.ethernet eth0: Link is Down > > [ 23.535604] ravb 11c30000.ethernet eth1: device will be stopped after > h/w processes are done. > > [ 23.547267] ravb 11c30000.ethernet eth1: Link is Down > > [ 23.802667] Microchip KSZ9131 Gigabit PHY 11c20000.ethernet- > ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c20000.ethernet- > ffffffff:07, irq=POLL) > > [ 24.031711] ravb 11c30000.ethernet eth1: failed to switch device to > config mode > > RTNETLINK answers: Connection timed out > > > > EXIT|FAIL||[422391:42:32] Failed to bring up ETH1|| > > > > root@smarc-rzg2l:/rzg2l-test-scripts# > > Hm... :-/ > What if you only clear ECMR.RCPT but continue to set CSR0? We already seen, RCPT=0, RCSC=1 with similar Hardware checksum function like R-Car, System crashes. Regards, Biju > > MBR, Sergey
On 10/12/21 9:23 PM, Biju Das wrote: >>>>> This patch enables Receive/Transmit port of TOE and removes the >>>>> setting of promiscuous bit from EMAC configuration mode register. >>>>> >>>>> This patch also update EMAC configuration mode comment from "PAUSE >>>>> prohibition" to "EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC >>>>> Pass Through". >>>> >>>> I'm not sure why you set ECMR.RCPT while you don't have the >>>> checksum offloaded... >>>> >>>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> >>>>> --- >>>>> v2->v3: >>>>> * Enabled TPE/RPE of TOE, as disabling causes loopback test to fail >>>>> * Documented CSR0 register bits >>>>> * Removed PRM setting from EMAC configuration mode >>>>> * Updated EMAC configuration mode. >>>>> v1->v2: >>>>> * No change >>>>> V1: >>>>> * New patch. >>>>> --- >>>>> drivers/net/ethernet/renesas/ravb.h | 6 ++++++ >>>>> drivers/net/ethernet/renesas/ravb_main.c | 5 +++-- >>>>> 2 files changed, 9 insertions(+), 2 deletions(-) >>>>> >>>>> diff --git a/drivers/net/ethernet/renesas/ravb.h >>>>> b/drivers/net/ethernet/renesas/ravb.h >>>>> index 69a771526776..08062d73df10 100644 >>>>> --- a/drivers/net/ethernet/renesas/ravb.h >>>>> +++ b/drivers/net/ethernet/renesas/ravb.h >>>>> @@ -204,6 +204,7 @@ enum ravb_reg { >>>>> TLFRCR = 0x0758, >>>>> RFCR = 0x0760, >>>>> MAFCR = 0x0778, >>>>> + CSR0 = 0x0800, /* RZ/G2L only */ >>>>> }; >>>>> >>>>> >>>>> @@ -964,6 +965,11 @@ enum CXR31_BIT { >>>>> CXR31_SEL_LINK1 = 0x00000008, >>>>> }; >>>>> >>>>> +enum CSR0_BIT { >>>>> + CSR0_TPE = 0x00000010, >>>>> + CSR0_RPE = 0x00000020, >>>>> +}; >>>>> + >>>> >>>> Is this really needed if you have ECMR.RCPT cleared? >>> >>> Yes it is required. Please see the current log and log with the >>> changes you suggested >>> >>> root@smarc-rzg2l:/rzg2l-test-scripts# ./eth_t_001.sh >>> [ 39.646891] ravb 11c20000.ethernet eth0: Link is Down >>> [ 39.715127] ravb 11c30000.ethernet eth1: Link is Down >>> [ 39.895680] Microchip KSZ9131 Gigabit PHY 11c20000.ethernet- >> ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c20000.ethernet- >> ffffffff:07, irq=POLL) >>> [ 39.966370] Microchip KSZ9131 Gigabit PHY 11c30000.ethernet- >> ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c30000.ethernet- >> ffffffff:07, irq=POLL) >>> [ 42.988573] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready >>> [ 42.995119] ravb 11c20000.ethernet eth0: Link is Up - 1Gbps/Full - >> flow control off >>> [ 43.052541] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready >>> [ 43.055710] ravb 11c30000.ethernet eth1: Link is Up - 1Gbps/Full - >> flow control off >>> >>> EXIT|PASS||[422391:43:00] || >>> >>> root@smarc-rzg2l:/rzg2l-test-scripts# >>> >>> >>> with the changes you suggested >>> ---------------------------- >>> >>> root@smarc-rzg2l:/rzg2l-test-scripts# ./eth_t_001.sh >>> [ 23.300520] ravb 11c20000.ethernet eth0: Link is Down >>> [ 23.535604] ravb 11c30000.ethernet eth1: device will be stopped after >> h/w processes are done. >>> [ 23.547267] ravb 11c30000.ethernet eth1: Link is Down >>> [ 23.802667] Microchip KSZ9131 Gigabit PHY 11c20000.ethernet- >> ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c20000.ethernet- >> ffffffff:07, irq=POLL) >>> [ 24.031711] ravb 11c30000.ethernet eth1: failed to switch device to >> config mode >>> RTNETLINK answers: Connection timed out >>> >>> EXIT|FAIL||[422391:42:32] Failed to bring up ETH1|| >>> >>> root@smarc-rzg2l:/rzg2l-test-scripts# >> >> Hm... :-/ >> What if you only clear ECMR.RCPT but continue to set CSR0? > > We already seen, RCPT=0, RCSC=1 with similar Hardware checksum function like R-Car, > System crashes. I didn't tell you to set ECMR.RCSC this time. :-) > Regards, > Biju MBR, Sergey
Hi Sergey, Thanks for the feedback. > Subject: Re: [PATCH net-next v3 13/14] ravb: Update ravb_emac_init_gbeth() > > On 10/12/21 9:23 PM, Biju Das wrote: > > >>>>> This patch enables Receive/Transmit port of TOE and removes the > >>>>> setting of promiscuous bit from EMAC configuration mode register. > >>>>> > >>>>> This patch also update EMAC configuration mode comment from "PAUSE > >>>>> prohibition" to "EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC > >>>>> Pass Through". > >>>> > >>>> I'm not sure why you set ECMR.RCPT while you don't have the > >>>> checksum offloaded... > >>>> > >>>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > >>>>> --- > >>>>> v2->v3: > >>>>> * Enabled TPE/RPE of TOE, as disabling causes loopback test to > >>>>> fail > >>>>> * Documented CSR0 register bits > >>>>> * Removed PRM setting from EMAC configuration mode > >>>>> * Updated EMAC configuration mode. > >>>>> v1->v2: > >>>>> * No change > >>>>> V1: > >>>>> * New patch. > >>>>> --- > >>>>> drivers/net/ethernet/renesas/ravb.h | 6 ++++++ > >>>>> drivers/net/ethernet/renesas/ravb_main.c | 5 +++-- > >>>>> 2 files changed, 9 insertions(+), 2 deletions(-) > >>>>> > >>>>> diff --git a/drivers/net/ethernet/renesas/ravb.h > >>>>> b/drivers/net/ethernet/renesas/ravb.h > >>>>> index 69a771526776..08062d73df10 100644 > >>>>> --- a/drivers/net/ethernet/renesas/ravb.h > >>>>> +++ b/drivers/net/ethernet/renesas/ravb.h > >>>>> @@ -204,6 +204,7 @@ enum ravb_reg { > >>>>> TLFRCR = 0x0758, > >>>>> RFCR = 0x0760, > >>>>> MAFCR = 0x0778, > >>>>> + CSR0 = 0x0800, /* RZ/G2L only */ > >>>>> }; > >>>>> > >>>>> > >>>>> @@ -964,6 +965,11 @@ enum CXR31_BIT { > >>>>> CXR31_SEL_LINK1 = 0x00000008, > >>>>> }; > >>>>> > >>>>> +enum CSR0_BIT { > >>>>> + CSR0_TPE = 0x00000010, > >>>>> + CSR0_RPE = 0x00000020, > >>>>> +}; > >>>>> + > >>>> > >>>> Is this really needed if you have ECMR.RCPT cleared? > >>> > >>> Yes it is required. Please see the current log and log with the > >>> changes you suggested > >>> > >>> root@smarc-rzg2l:/rzg2l-test-scripts# ./eth_t_001.sh > >>> [ 39.646891] ravb 11c20000.ethernet eth0: Link is Down > >>> [ 39.715127] ravb 11c30000.ethernet eth1: Link is Down > >>> [ 39.895680] Microchip KSZ9131 Gigabit PHY 11c20000.ethernet- > >> ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c20000.ethernet- > >> ffffffff:07, irq=POLL) > >>> [ 39.966370] Microchip KSZ9131 Gigabit PHY 11c30000.ethernet- > >> ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c30000.ethernet- > >> ffffffff:07, irq=POLL) > >>> [ 42.988573] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready > >>> [ 42.995119] ravb 11c20000.ethernet eth0: Link is Up - 1Gbps/Full - > >> flow control off > >>> [ 43.052541] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready > >>> [ 43.055710] ravb 11c30000.ethernet eth1: Link is Up - 1Gbps/Full - > >> flow control off > >>> > >>> EXIT|PASS||[422391:43:00] || > >>> > >>> root@smarc-rzg2l:/rzg2l-test-scripts# > >>> > >>> > >>> with the changes you suggested > >>> ---------------------------- > >>> > >>> root@smarc-rzg2l:/rzg2l-test-scripts# ./eth_t_001.sh > >>> [ 23.300520] ravb 11c20000.ethernet eth0: Link is Down > >>> [ 23.535604] ravb 11c30000.ethernet eth1: device will be stopped > after > >> h/w processes are done. > >>> [ 23.547267] ravb 11c30000.ethernet eth1: Link is Down > >>> [ 23.802667] Microchip KSZ9131 Gigabit PHY 11c20000.ethernet- > >> ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c20000.ethernet- > >> ffffffff:07, irq=POLL) > >>> [ 24.031711] ravb 11c30000.ethernet eth1: failed to switch device to > >> config mode > >>> RTNETLINK answers: Connection timed out > >>> > >>> EXIT|FAIL||[422391:42:32] Failed to bring up ETH1|| > >>> > >>> root@smarc-rzg2l:/rzg2l-test-scripts# > >> > >> Hm... :-/ > >> What if you only clear ECMR.RCPT but continue to set CSR0? > > > > We already seen, RCPT=0, RCSC=1 with similar Hardware checksum > > function like R-Car, System crashes. > > I didn't tell you to set ECMR.RCSC this time. :-) Theoretically, It should work as it is. As we are not doing any hardware checksum, H/W is just passing RX CSUM to TOE without any software intervention. It is clearly mentioned in data sheet, it is HW controlled. 25 RCPT B’0 R/W Reception CRC Pass Through 1: CRC of received frame is transferred to TOE. RCSC (auto calculation of checksum of received frame data part) function is disabled at this time. 0: CRC of received frame is not transferred to TOE. Regards, Biju > > > Regards, > > Biju > > MBR, Sergey
Hi Sergey, > Subject: RE: [PATCH net-next v3 13/14] ravb: Update ravb_emac_init_gbeth() > > Hi Sergey, > > Thanks for the feedback. > > > Subject: Re: [PATCH net-next v3 13/14] ravb: Update > > ravb_emac_init_gbeth() > > > > On 10/12/21 9:23 PM, Biju Das wrote: > > > > >>>>> This patch enables Receive/Transmit port of TOE and removes the > > >>>>> setting of promiscuous bit from EMAC configuration mode register. > > >>>>> > > >>>>> This patch also update EMAC configuration mode comment from > > >>>>> "PAUSE prohibition" to "EMAC Mode: PAUSE prohibition; Duplex; > > >>>>> TX; RX; CRC Pass Through". > > >>>> > > >>>> I'm not sure why you set ECMR.RCPT while you don't have the > > >>>> checksum offloaded... > > >>>> > > >>>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > >>>>> --- > > >>>>> v2->v3: > > >>>>> * Enabled TPE/RPE of TOE, as disabling causes loopback test to > > >>>>> fail > > >>>>> * Documented CSR0 register bits > > >>>>> * Removed PRM setting from EMAC configuration mode > > >>>>> * Updated EMAC configuration mode. > > >>>>> v1->v2: > > >>>>> * No change > > >>>>> V1: > > >>>>> * New patch. > > >>>>> --- > > >>>>> drivers/net/ethernet/renesas/ravb.h | 6 ++++++ > > >>>>> drivers/net/ethernet/renesas/ravb_main.c | 5 +++-- > > >>>>> 2 files changed, 9 insertions(+), 2 deletions(-) > > >>>>> > > >>>>> diff --git a/drivers/net/ethernet/renesas/ravb.h > > >>>>> b/drivers/net/ethernet/renesas/ravb.h > > >>>>> index 69a771526776..08062d73df10 100644 > > >>>>> --- a/drivers/net/ethernet/renesas/ravb.h > > >>>>> +++ b/drivers/net/ethernet/renesas/ravb.h > > >>>>> @@ -204,6 +204,7 @@ enum ravb_reg { > > >>>>> TLFRCR = 0x0758, > > >>>>> RFCR = 0x0760, > > >>>>> MAFCR = 0x0778, > > >>>>> + CSR0 = 0x0800, /* RZ/G2L only */ > > >>>>> }; > > >>>>> > > >>>>> > > >>>>> @@ -964,6 +965,11 @@ enum CXR31_BIT { > > >>>>> CXR31_SEL_LINK1 = 0x00000008, > > >>>>> }; > > >>>>> > > >>>>> +enum CSR0_BIT { > > >>>>> + CSR0_TPE = 0x00000010, > > >>>>> + CSR0_RPE = 0x00000020, > > >>>>> +}; > > >>>>> + > > >>>> > > >>>> Is this really needed if you have ECMR.RCPT cleared? > > >>> > > >>> Yes it is required. Please see the current log and log with the > > >>> changes you suggested > > >>> > > >>> root@smarc-rzg2l:/rzg2l-test-scripts# ./eth_t_001.sh > > >>> [ 39.646891] ravb 11c20000.ethernet eth0: Link is Down > > >>> [ 39.715127] ravb 11c30000.ethernet eth1: Link is Down > > >>> [ 39.895680] Microchip KSZ9131 Gigabit PHY 11c20000.ethernet- > > >> ffffffff:07: attached PHY driver > > >> (mii_bus:phy_addr=11c20000.ethernet- > > >> ffffffff:07, irq=POLL) > > >>> [ 39.966370] Microchip KSZ9131 Gigabit PHY 11c30000.ethernet- > > >> ffffffff:07: attached PHY driver > > >> (mii_bus:phy_addr=11c30000.ethernet- > > >> ffffffff:07, irq=POLL) > > >>> [ 42.988573] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes > ready > > >>> [ 42.995119] ravb 11c20000.ethernet eth0: Link is Up - 1Gbps/Full > - > > >> flow control off > > >>> [ 43.052541] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes > ready > > >>> [ 43.055710] ravb 11c30000.ethernet eth1: Link is Up - 1Gbps/Full > - > > >> flow control off > > >>> > > >>> EXIT|PASS||[422391:43:00] || > > >>> > > >>> root@smarc-rzg2l:/rzg2l-test-scripts# > > >>> > > >>> > > >>> with the changes you suggested > > >>> ---------------------------- > > >>> > > >>> root@smarc-rzg2l:/rzg2l-test-scripts# ./eth_t_001.sh > > >>> [ 23.300520] ravb 11c20000.ethernet eth0: Link is Down > > >>> [ 23.535604] ravb 11c30000.ethernet eth1: device will be stopped > > after > > >> h/w processes are done. > > >>> [ 23.547267] ravb 11c30000.ethernet eth1: Link is Down > > >>> [ 23.802667] Microchip KSZ9131 Gigabit PHY 11c20000.ethernet- > > >> ffffffff:07: attached PHY driver > > >> (mii_bus:phy_addr=11c20000.ethernet- > > >> ffffffff:07, irq=POLL) > > >>> [ 24.031711] ravb 11c30000.ethernet eth1: failed to switch device > to > > >> config mode > > >>> RTNETLINK answers: Connection timed out > > >>> > > >>> EXIT|FAIL||[422391:42:32] Failed to bring up ETH1|| > > >>> > > >>> root@smarc-rzg2l:/rzg2l-test-scripts# > > >> > > >> Hm... :-/ > > >> What if you only clear ECMR.RCPT but continue to set CSR0? > > > > > > We already seen, RCPT=0, RCSC=1 with similar Hardware checksum > > > function like R-Car, System crashes. > > > > I didn't tell you to set ECMR.RCSC this time. :-) > > Theoretically, It should work as it is. As we are not doing any hardware > checksum, > > H/W is just passing RX CSUM to TOE without any software intervention. > > It is clearly mentioned in data sheet, it is HW controlled. > > 25 RCPT B’0 R/W Reception CRC Pass Through > 1: CRC of received frame is transferred to TOE. > RCSC (auto calculation of checksum of received frame data part) function > is disabled at this time. > 0: CRC of received frame is not transferred to TOE. > The board doesn't boot with NFS, if I take out RCPT. So it is needed
On 10/12/21 9:55 PM, Biju Das wrote: [...] >>>>>>> This patch enables Receive/Transmit port of TOE and removes the >>>>>>> setting of promiscuous bit from EMAC configuration mode register. >>>>>>> >>>>>>> This patch also update EMAC configuration mode comment from "PAUSE >>>>>>> prohibition" to "EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC >>>>>>> Pass Through". >>>>>> >>>>>> I'm not sure why you set ECMR.RCPT while you don't have the >>>>>> checksum offloaded... >>>>>> >>>>>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> >>>>>>> --- >>>>>>> v2->v3: >>>>>>> * Enabled TPE/RPE of TOE, as disabling causes loopback test to >>>>>>> fail >>>>>>> * Documented CSR0 register bits >>>>>>> * Removed PRM setting from EMAC configuration mode >>>>>>> * Updated EMAC configuration mode. >>>>>>> v1->v2: >>>>>>> * No change >>>>>>> V1: >>>>>>> * New patch. >>>>>>> --- >>>>>>> drivers/net/ethernet/renesas/ravb.h | 6 ++++++ >>>>>>> drivers/net/ethernet/renesas/ravb_main.c | 5 +++-- >>>>>>> 2 files changed, 9 insertions(+), 2 deletions(-) >>>>>>> >>>>>>> diff --git a/drivers/net/ethernet/renesas/ravb.h >>>>>>> b/drivers/net/ethernet/renesas/ravb.h >>>>>>> index 69a771526776..08062d73df10 100644 >>>>>>> --- a/drivers/net/ethernet/renesas/ravb.h >>>>>>> +++ b/drivers/net/ethernet/renesas/ravb.h >>>>>>> @@ -204,6 +204,7 @@ enum ravb_reg { >>>>>>> TLFRCR = 0x0758, >>>>>>> RFCR = 0x0760, >>>>>>> MAFCR = 0x0778, >>>>>>> + CSR0 = 0x0800, /* RZ/G2L only */ >>>>>>> }; >>>>>>> >>>>>>> >>>>>>> @@ -964,6 +965,11 @@ enum CXR31_BIT { >>>>>>> CXR31_SEL_LINK1 = 0x00000008, >>>>>>> }; >>>>>>> >>>>>>> +enum CSR0_BIT { >>>>>>> + CSR0_TPE = 0x00000010, >>>>>>> + CSR0_RPE = 0x00000020, >>>>>>> +}; >>>>>>> + >>>>>> >>>>>> Is this really needed if you have ECMR.RCPT cleared? >>>>> >>>>> Yes it is required. Please see the current log and log with the >>>>> changes you suggested >>>>> >>>>> root@smarc-rzg2l:/rzg2l-test-scripts# ./eth_t_001.sh >>>>> [ 39.646891] ravb 11c20000.ethernet eth0: Link is Down >>>>> [ 39.715127] ravb 11c30000.ethernet eth1: Link is Down >>>>> [ 39.895680] Microchip KSZ9131 Gigabit PHY 11c20000.ethernet- >>>> ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c20000.ethernet- >>>> ffffffff:07, irq=POLL) >>>>> [ 39.966370] Microchip KSZ9131 Gigabit PHY 11c30000.ethernet- >>>> ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c30000.ethernet- >>>> ffffffff:07, irq=POLL) >>>>> [ 42.988573] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready >>>>> [ 42.995119] ravb 11c20000.ethernet eth0: Link is Up - 1Gbps/Full - >>>> flow control off >>>>> [ 43.052541] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready >>>>> [ 43.055710] ravb 11c30000.ethernet eth1: Link is Up - 1Gbps/Full - >>>> flow control off >>>>> >>>>> EXIT|PASS||[422391:43:00] || >>>>> >>>>> root@smarc-rzg2l:/rzg2l-test-scripts# >>>>> >>>>> >>>>> with the changes you suggested >>>>> ---------------------------- >>>>> >>>>> root@smarc-rzg2l:/rzg2l-test-scripts# ./eth_t_001.sh >>>>> [ 23.300520] ravb 11c20000.ethernet eth0: Link is Down >>>>> [ 23.535604] ravb 11c30000.ethernet eth1: device will be stopped >> after >>>> h/w processes are done. >>>>> [ 23.547267] ravb 11c30000.ethernet eth1: Link is Down >>>>> [ 23.802667] Microchip KSZ9131 Gigabit PHY 11c20000.ethernet- >>>> ffffffff:07: attached PHY driver (mii_bus:phy_addr=11c20000.ethernet- >>>> ffffffff:07, irq=POLL) >>>>> [ 24.031711] ravb 11c30000.ethernet eth1: failed to switch device to >>>> config mode >>>>> RTNETLINK answers: Connection timed out >>>>> >>>>> EXIT|FAIL||[422391:42:32] Failed to bring up ETH1|| >>>>> >>>>> root@smarc-rzg2l:/rzg2l-test-scripts# >>>> >>>> Hm... :-/ >>>> What if you only clear ECMR.RCPT but continue to set CSR0? >>> >>> We already seen, RCPT=0, RCSC=1 with similar Hardware checksum >>> function like R-Car, System crashes. >> >> I didn't tell you to set ECMR.RCSC this time. :-) > > Theoretically, It should work as it is. As we are not doing any hardware checksum, > > H/W is just passing RX CSUM to TOE without any software intervention. > > It is clearly mentioned in data sheet, it is HW controlled. > > 25 RCPT B’0 R/W Reception CRC Pass Through > 1: CRC of received frame is transferred to TOE. > RCSC (auto calculation of checksum of received frame data part) function is disabled > at this time. > 0: CRC of received frame is not transferred to TOE. Ah, I think it's the (usual) checksum-vs-CRC mixup. I don't know why TOE needs CRC tho but it's 4 bytes at the end of a frame, not having much toi do with the 2-byte checksums... > Regards, > Biju [...] MBR, Sergey
On 10/13/21 6:57 PM, Jakub Kicinski wrote: >> Ah, I think it's the (usual) checksum-vs-CRC mixup. I don't know >> why TOE needs CRC tho but it's 4 bytes at the end of a frame, not >> having much toi do with the 2-byte checksums... s/toi/to/. > Meaning v3 is good as is? I'm trying understand if I should apply it ;) Yes, I'm giving up (-: Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru> MBR, Sergey
diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index 69a771526776..08062d73df10 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -204,6 +204,7 @@ enum ravb_reg { TLFRCR = 0x0758, RFCR = 0x0760, MAFCR = 0x0778, + CSR0 = 0x0800, /* RZ/G2L only */ }; @@ -964,6 +965,11 @@ enum CXR31_BIT { CXR31_SEL_LINK1 = 0x00000008, }; +enum CSR0_BIT { + CSR0_TPE = 0x00000010, + CSR0_RPE = 0x00000020, +}; + #define DBAT_ENTRY_NUM 22 #define RX_QUEUE_OFFSET 4 #define NUM_RX_QUEUE 2 diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 21fb83f209d5..f3f676e433d1 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -519,10 +519,10 @@ static void ravb_emac_init_gbeth(struct net_device *ndev) /* Receive frame limit set register */ ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR); - /* PAUSE prohibition */ + /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | ECMR_TE | ECMR_RE | ECMR_RCPT | - ECMR_TXF | ECMR_RXF | ECMR_PRM, ECMR); + ECMR_TXF | ECMR_RXF, ECMR); ravb_set_rate_gbeth(ndev); @@ -534,6 +534,7 @@ static void ravb_emac_init_gbeth(struct net_device *ndev) /* E-MAC status register clear */ ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); + ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); /* E-MAC interrupt enable register */ ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);
This patch enables Receive/Transmit port of TOE and removes the setting of promiscuous bit from EMAC configuration mode register. This patch also update EMAC configuration mode comment from "PAUSE prohibition" to "EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through". Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v2->v3: * Enabled TPE/RPE of TOE, as disabling causes loopback test to fail * Documented CSR0 register bits * Removed PRM setting from EMAC configuration mode * Updated EMAC configuration mode. v1->v2: * No change V1: * New patch. --- drivers/net/ethernet/renesas/ravb.h | 6 ++++++ drivers/net/ethernet/renesas/ravb_main.c | 5 +++-- 2 files changed, 9 insertions(+), 2 deletions(-)