Message ID | 20211011112719.3951784-5-claudiu.beznea@microchip.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | clk: at91: updates for power management and dvfs | expand |
On 11/10/2021 at 13:27, Claudiu Beznea wrote: > SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the > register at offset 0x30 (relative to PMC). In the last/first phase of > suspend/resume procedure (which is architecture specific) the parent > of master clocks are changed (via assembly code) for more power saving > (see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable > and at91_mckx_ps_restore). Thus the macros corresponding to register > at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S. > commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's > master clock") introduced the proper macros but didn't adapted the > clk-master.c as well. Thus, this commit adapt the clk-master.c to use > the macros introduced in commit ec03f18cc222 ("clk: at91: add register > definition for sama7g5's master clock"). > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> > --- > drivers/clk/at91/clk-master.c | 50 ++++++++++++++++------------------- > 1 file changed, 23 insertions(+), 27 deletions(-) > > diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c > index f75549fff023..88f7af1bfff6 100644 > --- a/drivers/clk/at91/clk-master.c > +++ b/drivers/clk/at91/clk-master.c > @@ -17,15 +17,7 @@ > #define MASTER_DIV_SHIFT 8 > #define MASTER_DIV_MASK 0x7 > > -#define PMC_MCR 0x30 > -#define PMC_MCR_ID_MSK GENMASK(3, 0) > -#define PMC_MCR_CMD BIT(7) > -#define PMC_MCR_DIV GENMASK(10, 8) > -#define PMC_MCR_CSS GENMASK(20, 16) > #define PMC_MCR_CSS_SHIFT (16) > -#define PMC_MCR_EN BIT(28) > - > -#define PMC_MCR_ID(x) ((x) & PMC_MCR_ID_MSK) > > #define MASTER_MAX_ID 4 > > @@ -687,20 +679,22 @@ static void clk_sama7g5_master_set(struct clk_master *master, > { > unsigned long flags; > unsigned int val, cparent; > - unsigned int enable = status ? PMC_MCR_EN : 0; > + unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0; > > spin_lock_irqsave(master->lock, flags); > > - regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id)); > - regmap_read(master->regmap, PMC_MCR, &val); > - regmap_update_bits(master->regmap, PMC_MCR, > - enable | PMC_MCR_CSS | PMC_MCR_DIV | > - PMC_MCR_CMD | PMC_MCR_ID_MSK, > + regmap_write(master->regmap, AT91_PMC_MCR_V2, > + AT91_PMC_MCR_V2_ID(master->id)); > + regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); > + regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, > + enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV | > + AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK, > enable | (master->parent << PMC_MCR_CSS_SHIFT) | > (master->div << MASTER_DIV_SHIFT) | > - PMC_MCR_CMD | PMC_MCR_ID(master->id)); > + AT91_PMC_MCR_V2_CMD | > + AT91_PMC_MCR_V2_ID(master->id)); > > - cparent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT; > + cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; > > /* Wait here only if parent is being changed. */ > while ((cparent != master->parent) && !clk_master_ready(master)) > @@ -725,10 +719,12 @@ static void clk_sama7g5_master_disable(struct clk_hw *hw) > > spin_lock_irqsave(master->lock, flags); > > - regmap_write(master->regmap, PMC_MCR, master->id); > - regmap_update_bits(master->regmap, PMC_MCR, > - PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK, > - PMC_MCR_CMD | PMC_MCR_ID(master->id)); > + regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); > + regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, > + AT91_PMC_MCR_V2_EN | AT91_PMC_MCR_V2_CMD | > + AT91_PMC_MCR_V2_ID_MSK, > + AT91_PMC_MCR_V2_CMD | > + AT91_PMC_MCR_V2_ID(master->id)); > > spin_unlock_irqrestore(master->lock, flags); > } > @@ -741,12 +737,12 @@ static int clk_sama7g5_master_is_enabled(struct clk_hw *hw) > > spin_lock_irqsave(master->lock, flags); > > - regmap_write(master->regmap, PMC_MCR, master->id); > - regmap_read(master->regmap, PMC_MCR, &val); > + regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); > + regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); > > spin_unlock_irqrestore(master->lock, flags); > > - return !!(val & PMC_MCR_EN); > + return !!(val & AT91_PMC_MCR_V2_EN); > } > > static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate, > @@ -842,10 +838,10 @@ at91_clk_sama7g5_register_master(struct regmap *regmap, > master->mux_table = mux_table; > > spin_lock_irqsave(master->lock, flags); > - regmap_write(master->regmap, PMC_MCR, master->id); > - regmap_read(master->regmap, PMC_MCR, &val); > - master->parent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT; > - master->div = (val & PMC_MCR_DIV) >> MASTER_DIV_SHIFT; > + regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); > + regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); > + master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; > + master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT; > spin_unlock_irqrestore(master->lock, flags); > > hw = &master->hw; >
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index f75549fff023..88f7af1bfff6 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -17,15 +17,7 @@ #define MASTER_DIV_SHIFT 8 #define MASTER_DIV_MASK 0x7 -#define PMC_MCR 0x30 -#define PMC_MCR_ID_MSK GENMASK(3, 0) -#define PMC_MCR_CMD BIT(7) -#define PMC_MCR_DIV GENMASK(10, 8) -#define PMC_MCR_CSS GENMASK(20, 16) #define PMC_MCR_CSS_SHIFT (16) -#define PMC_MCR_EN BIT(28) - -#define PMC_MCR_ID(x) ((x) & PMC_MCR_ID_MSK) #define MASTER_MAX_ID 4 @@ -687,20 +679,22 @@ static void clk_sama7g5_master_set(struct clk_master *master, { unsigned long flags; unsigned int val, cparent; - unsigned int enable = status ? PMC_MCR_EN : 0; + unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0; spin_lock_irqsave(master->lock, flags); - regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id)); - regmap_read(master->regmap, PMC_MCR, &val); - regmap_update_bits(master->regmap, PMC_MCR, - enable | PMC_MCR_CSS | PMC_MCR_DIV | - PMC_MCR_CMD | PMC_MCR_ID_MSK, + regmap_write(master->regmap, AT91_PMC_MCR_V2, + AT91_PMC_MCR_V2_ID(master->id)); + regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); + regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, + enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV | + AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK, enable | (master->parent << PMC_MCR_CSS_SHIFT) | (master->div << MASTER_DIV_SHIFT) | - PMC_MCR_CMD | PMC_MCR_ID(master->id)); + AT91_PMC_MCR_V2_CMD | + AT91_PMC_MCR_V2_ID(master->id)); - cparent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT; + cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; /* Wait here only if parent is being changed. */ while ((cparent != master->parent) && !clk_master_ready(master)) @@ -725,10 +719,12 @@ static void clk_sama7g5_master_disable(struct clk_hw *hw) spin_lock_irqsave(master->lock, flags); - regmap_write(master->regmap, PMC_MCR, master->id); - regmap_update_bits(master->regmap, PMC_MCR, - PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK, - PMC_MCR_CMD | PMC_MCR_ID(master->id)); + regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); + regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, + AT91_PMC_MCR_V2_EN | AT91_PMC_MCR_V2_CMD | + AT91_PMC_MCR_V2_ID_MSK, + AT91_PMC_MCR_V2_CMD | + AT91_PMC_MCR_V2_ID(master->id)); spin_unlock_irqrestore(master->lock, flags); } @@ -741,12 +737,12 @@ static int clk_sama7g5_master_is_enabled(struct clk_hw *hw) spin_lock_irqsave(master->lock, flags); - regmap_write(master->regmap, PMC_MCR, master->id); - regmap_read(master->regmap, PMC_MCR, &val); + regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); + regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); spin_unlock_irqrestore(master->lock, flags); - return !!(val & PMC_MCR_EN); + return !!(val & AT91_PMC_MCR_V2_EN); } static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate, @@ -842,10 +838,10 @@ at91_clk_sama7g5_register_master(struct regmap *regmap, master->mux_table = mux_table; spin_lock_irqsave(master->lock, flags); - regmap_write(master->regmap, PMC_MCR, master->id); - regmap_read(master->regmap, PMC_MCR, &val); - master->parent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT; - master->div = (val & PMC_MCR_DIV) >> MASTER_DIV_SHIFT; + regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); + regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); + master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; + master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT; spin_unlock_irqrestore(master->lock, flags); hw = &master->hw;
SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the register at offset 0x30 (relative to PMC). In the last/first phase of suspend/resume procedure (which is architecture specific) the parent of master clocks are changed (via assembly code) for more power saving (see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable and at91_mckx_ps_restore). Thus the macros corresponding to register at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S. commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's master clock") introduced the proper macros but didn't adapted the clk-master.c as well. Thus, this commit adapt the clk-master.c to use the macros introduced in commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's master clock"). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> --- drivers/clk/at91/clk-master.c | 50 ++++++++++++++++------------------- 1 file changed, 23 insertions(+), 27 deletions(-)