diff mbox series

[v4,2/2,RFT] clk: samsung: exynos5433: update apollo and atlas clock probing

Message ID 20211014195347.3635601-3-willmcvicker@google.com (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series clk: samsung: add common support for CPU clocks | expand

Commit Message

William McVicker Oct. 14, 2021, 7:53 p.m. UTC 
Use the samsung common clk driver to initialize the apollo and atlas
clocks. This removes their custom init functions and uses the
samsung_cmu_register_one() instead.

Signed-off-by: Will McVicker <willmcvicker@google.com>
---
 drivers/clk/samsung/clk-exynos5433.c | 120 +++++++++++----------------
 1 file changed, 48 insertions(+), 72 deletions(-)

Comments

Marek Szyprowski Oct. 15, 2021, 7:15 a.m. UTC | #1 
On 14.10.2021 21:53, Will McVicker wrote:
> Use the samsung common clk driver to initialize the apollo and atlas
> clocks. This removes their custom init functions and uses the
> samsung_cmu_register_one() instead.
>
> Signed-off-by: Will McVicker <willmcvicker@google.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>   drivers/clk/samsung/clk-exynos5433.c | 120 +++++++++++----------------
>   1 file changed, 48 insertions(+), 72 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
> index f203074d858b..cec66d2a4ee2 100644
> --- a/drivers/clk/samsung/clk-exynos5433.c
> +++ b/drivers/clk/samsung/clk-exynos5433.c
> @@ -3675,44 +3675,32 @@ static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst
>   	{  0 },
>   };
>   
> +static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = {
> +	CPU_CLK(CLK_SCLK_APOLLO, "apolloclk", CLK_MOUT_APOLLO_PLL,
> +			CLK_MOUT_BUS_PLL_APOLLO_USER,
> +			CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200,
> +			exynos5433_apolloclk_d),
> +};
> +
> +static const struct samsung_cmu_info apollo_cmu_info __initconst = {
> +	.pll_clks	= apollo_pll_clks,
> +	.nr_pll_clks	= ARRAY_SIZE(apollo_pll_clks),
> +	.mux_clks	= apollo_mux_clks,
> +	.nr_mux_clks	= ARRAY_SIZE(apollo_mux_clks),
> +	.div_clks	= apollo_div_clks,
> +	.nr_div_clks	= ARRAY_SIZE(apollo_div_clks),
> +	.gate_clks	= apollo_gate_clks,
> +	.nr_gate_clks	= ARRAY_SIZE(apollo_gate_clks),
> +	.cpu_clks	= apollo_cpu_clks,
> +	.nr_cpu_clks	= ARRAY_SIZE(apollo_cpu_clks),
> +	.nr_clk_ids	= APOLLO_NR_CLK,
> +	.clk_regs	= apollo_clk_regs,
> +	.nr_clk_regs	= ARRAY_SIZE(apollo_clk_regs),
> +};
> +
>   static void __init exynos5433_cmu_apollo_init(struct device_node *np)
>   {
> -	void __iomem *reg_base;
> -	struct samsung_clk_provider *ctx;
> -	struct clk_hw **hws;
> -
> -	reg_base = of_iomap(np, 0);
> -	if (!reg_base) {
> -		panic("%s: failed to map registers\n", __func__);
> -		return;
> -	}
> -
> -	ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK);
> -	if (!ctx) {
> -		panic("%s: unable to allocate ctx\n", __func__);
> -		return;
> -	}
> -
> -	samsung_clk_register_pll(ctx, apollo_pll_clks,
> -				 ARRAY_SIZE(apollo_pll_clks), reg_base);
> -	samsung_clk_register_mux(ctx, apollo_mux_clks,
> -				 ARRAY_SIZE(apollo_mux_clks));
> -	samsung_clk_register_div(ctx, apollo_div_clks,
> -				 ARRAY_SIZE(apollo_div_clks));
> -	samsung_clk_register_gate(ctx, apollo_gate_clks,
> -				  ARRAY_SIZE(apollo_gate_clks));
> -
> -	hws = ctx->clk_data.hws;
> -
> -	exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
> -		hws[CLK_MOUT_APOLLO_PLL], hws[CLK_MOUT_BUS_PLL_APOLLO_USER], 0x200,
> -		exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
> -		CLK_CPU_HAS_E5433_REGS_LAYOUT);
> -
> -	samsung_clk_sleep_init(reg_base, apollo_clk_regs,
> -			       ARRAY_SIZE(apollo_clk_regs));
> -
> -	samsung_clk_of_add_provider(np, ctx);
> +	samsung_cmu_register_one(np, &apollo_cmu_info);
>   }
>   CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
>   		exynos5433_cmu_apollo_init);
> @@ -3932,44 +3920,32 @@ static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst =
>   	{  0 },
>   };
>   
> -static void __init exynos5433_cmu_atlas_init(struct device_node *np)
> -{
> -	void __iomem *reg_base;
> -	struct samsung_clk_provider *ctx;
> -	struct clk_hw **hws;
> -
> -	reg_base = of_iomap(np, 0);
> -	if (!reg_base) {
> -		panic("%s: failed to map registers\n", __func__);
> -		return;
> -	}
> -
> -	ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK);
> -	if (!ctx) {
> -		panic("%s: unable to allocate ctx\n", __func__);
> -		return;
> -	}
> -
> -	samsung_clk_register_pll(ctx, atlas_pll_clks,
> -				 ARRAY_SIZE(atlas_pll_clks), reg_base);
> -	samsung_clk_register_mux(ctx, atlas_mux_clks,
> -				 ARRAY_SIZE(atlas_mux_clks));
> -	samsung_clk_register_div(ctx, atlas_div_clks,
> -				 ARRAY_SIZE(atlas_div_clks));
> -	samsung_clk_register_gate(ctx, atlas_gate_clks,
> -				  ARRAY_SIZE(atlas_gate_clks));
> -
> -	hws = ctx->clk_data.hws;
> -
> -	exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
> -		hws[CLK_MOUT_ATLAS_PLL], hws[CLK_MOUT_BUS_PLL_ATLAS_USER], 0x200,
> -		exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
> -		CLK_CPU_HAS_E5433_REGS_LAYOUT);
> +static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = {
> +	CPU_CLK(CLK_SCLK_ATLAS, "atlasclk", CLK_MOUT_ATLAS_PLL,
> +			CLK_MOUT_BUS_PLL_ATLAS_USER,
> +			CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200,
> +			exynos5433_atlasclk_d),
> +};
>   
> -	samsung_clk_sleep_init(reg_base, atlas_clk_regs,
> -			       ARRAY_SIZE(atlas_clk_regs));
> +static const struct samsung_cmu_info atlas_cmu_info __initconst = {
> +	.pll_clks	= atlas_pll_clks,
> +	.nr_pll_clks	= ARRAY_SIZE(atlas_pll_clks),
> +	.mux_clks	= atlas_mux_clks,
> +	.nr_mux_clks	= ARRAY_SIZE(atlas_mux_clks),
> +	.div_clks	= atlas_div_clks,
> +	.nr_div_clks	= ARRAY_SIZE(atlas_div_clks),
> +	.gate_clks	= atlas_gate_clks,
> +	.nr_gate_clks	= ARRAY_SIZE(atlas_gate_clks),
> +	.cpu_clks	= atlas_cpu_clks,
> +	.nr_cpu_clks	= ARRAY_SIZE(atlas_cpu_clks),
> +	.nr_clk_ids	= ATLAS_NR_CLK,
> +	.clk_regs	= atlas_clk_regs,
> +	.nr_clk_regs	= ARRAY_SIZE(atlas_clk_regs),
> +};
>   
> -	samsung_clk_of_add_provider(np, ctx);
> +static void __init exynos5433_cmu_atlas_init(struct device_node *np)
> +{
> +	samsung_cmu_register_one(np, &atlas_cmu_info);
>   }
>   CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
>   		exynos5433_cmu_atlas_init);

Best regards
Krzysztof Kozlowski Oct. 15, 2021, 10:14 a.m. UTC | #2 
On 14/10/2021 21:53, Will McVicker wrote:
> Use the samsung common clk driver to initialize the apollo and atlas
> clocks. This removes their custom init functions and uses the
> samsung_cmu_register_one() instead.
> 
> Signed-off-by: Will McVicker <willmcvicker@google.com>
> ---
>  drivers/clk/samsung/clk-exynos5433.c | 120 +++++++++++----------------
>  1 file changed, 48 insertions(+), 72 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
> index f203074d858b..cec66d2a4ee2 100644
> --- a/drivers/clk/samsung/clk-exynos5433.c
> +++ b/drivers/clk/samsung/clk-exynos5433.c
> @@ -3675,44 +3675,32 @@ static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst
>  	{  0 },
>  };


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>


Best regards,
Krzysztof
Sylwester Nawrocki Oct. 15, 2021, 3:09 p.m. UTC | #3 
On 14.10.2021 21:53, Will McVicker wrote:
> Use the samsung common clk driver to initialize the apollo and atlas
> clocks. This removes their custom init functions and uses the
> samsung_cmu_register_one() instead.
> 
> Signed-off-by: Will McVicker <willmcvicker@google.com>

Patch applied, thank you.
Chanwoo Choi Oct. 15, 2021, 11:10 p.m. UTC | #4 
On 21. 10. 15. 오전 4:53, Will McVicker wrote:
> Use the samsung common clk driver to initialize the apollo and atlas
> clocks. This removes their custom init functions and uses the
> samsung_cmu_register_one() instead.
> 
> Signed-off-by: Will McVicker <willmcvicker@google.com>
> ---
>   drivers/clk/samsung/clk-exynos5433.c | 120 +++++++++++----------------
>   1 file changed, 48 insertions(+), 72 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
> index f203074d858b..cec66d2a4ee2 100644
> --- a/drivers/clk/samsung/clk-exynos5433.c
> +++ b/drivers/clk/samsung/clk-exynos5433.c
> @@ -3675,44 +3675,32 @@ static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst
>   	{  0 },
>   };
>   
> +static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = {
> +	CPU_CLK(CLK_SCLK_APOLLO, "apolloclk", CLK_MOUT_APOLLO_PLL,
> +			CLK_MOUT_BUS_PLL_APOLLO_USER,
> +			CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200,
> +			exynos5433_apolloclk_d),
> +};
> +
> +static const struct samsung_cmu_info apollo_cmu_info __initconst = {
> +	.pll_clks	= apollo_pll_clks,
> +	.nr_pll_clks	= ARRAY_SIZE(apollo_pll_clks),
> +	.mux_clks	= apollo_mux_clks,
> +	.nr_mux_clks	= ARRAY_SIZE(apollo_mux_clks),
> +	.div_clks	= apollo_div_clks,
> +	.nr_div_clks	= ARRAY_SIZE(apollo_div_clks),
> +	.gate_clks	= apollo_gate_clks,
> +	.nr_gate_clks	= ARRAY_SIZE(apollo_gate_clks),
> +	.cpu_clks	= apollo_cpu_clks,
> +	.nr_cpu_clks	= ARRAY_SIZE(apollo_cpu_clks),
> +	.nr_clk_ids	= APOLLO_NR_CLK,
> +	.clk_regs	= apollo_clk_regs,
> +	.nr_clk_regs	= ARRAY_SIZE(apollo_clk_regs),
> +};
> +
>   static void __init exynos5433_cmu_apollo_init(struct device_node *np)
>   {
> -	void __iomem *reg_base;
> -	struct samsung_clk_provider *ctx;
> -	struct clk_hw **hws;
> -
> -	reg_base = of_iomap(np, 0);
> -	if (!reg_base) {
> -		panic("%s: failed to map registers\n", __func__);
> -		return;
> -	}
> -
> -	ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK);
> -	if (!ctx) {
> -		panic("%s: unable to allocate ctx\n", __func__);
> -		return;
> -	}
> -
> -	samsung_clk_register_pll(ctx, apollo_pll_clks,
> -				 ARRAY_SIZE(apollo_pll_clks), reg_base);
> -	samsung_clk_register_mux(ctx, apollo_mux_clks,
> -				 ARRAY_SIZE(apollo_mux_clks));
> -	samsung_clk_register_div(ctx, apollo_div_clks,
> -				 ARRAY_SIZE(apollo_div_clks));
> -	samsung_clk_register_gate(ctx, apollo_gate_clks,
> -				  ARRAY_SIZE(apollo_gate_clks));
> -
> -	hws = ctx->clk_data.hws;
> -
> -	exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
> -		hws[CLK_MOUT_APOLLO_PLL], hws[CLK_MOUT_BUS_PLL_APOLLO_USER], 0x200,
> -		exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
> -		CLK_CPU_HAS_E5433_REGS_LAYOUT);
> -
> -	samsung_clk_sleep_init(reg_base, apollo_clk_regs,
> -			       ARRAY_SIZE(apollo_clk_regs));
> -
> -	samsung_clk_of_add_provider(np, ctx);
> +	samsung_cmu_register_one(np, &apollo_cmu_info);
>   }
>   CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
>   		exynos5433_cmu_apollo_init);
> @@ -3932,44 +3920,32 @@ static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst =
>   	{  0 },
>   };
>   
> -static void __init exynos5433_cmu_atlas_init(struct device_node *np)
> -{
> -	void __iomem *reg_base;
> -	struct samsung_clk_provider *ctx;
> -	struct clk_hw **hws;
> -
> -	reg_base = of_iomap(np, 0);
> -	if (!reg_base) {
> -		panic("%s: failed to map registers\n", __func__);
> -		return;
> -	}
> -
> -	ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK);
> -	if (!ctx) {
> -		panic("%s: unable to allocate ctx\n", __func__);
> -		return;
> -	}
> -
> -	samsung_clk_register_pll(ctx, atlas_pll_clks,
> -				 ARRAY_SIZE(atlas_pll_clks), reg_base);
> -	samsung_clk_register_mux(ctx, atlas_mux_clks,
> -				 ARRAY_SIZE(atlas_mux_clks));
> -	samsung_clk_register_div(ctx, atlas_div_clks,
> -				 ARRAY_SIZE(atlas_div_clks));
> -	samsung_clk_register_gate(ctx, atlas_gate_clks,
> -				  ARRAY_SIZE(atlas_gate_clks));
> -
> -	hws = ctx->clk_data.hws;
> -
> -	exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
> -		hws[CLK_MOUT_ATLAS_PLL], hws[CLK_MOUT_BUS_PLL_ATLAS_USER], 0x200,
> -		exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
> -		CLK_CPU_HAS_E5433_REGS_LAYOUT);
> +static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = {
> +	CPU_CLK(CLK_SCLK_ATLAS, "atlasclk", CLK_MOUT_ATLAS_PLL,
> +			CLK_MOUT_BUS_PLL_ATLAS_USER,
> +			CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200,
> +			exynos5433_atlasclk_d),
> +};
>   
> -	samsung_clk_sleep_init(reg_base, atlas_clk_regs,
> -			       ARRAY_SIZE(atlas_clk_regs));
> +static const struct samsung_cmu_info atlas_cmu_info __initconst = {
> +	.pll_clks	= atlas_pll_clks,
> +	.nr_pll_clks	= ARRAY_SIZE(atlas_pll_clks),
> +	.mux_clks	= atlas_mux_clks,
> +	.nr_mux_clks	= ARRAY_SIZE(atlas_mux_clks),
> +	.div_clks	= atlas_div_clks,
> +	.nr_div_clks	= ARRAY_SIZE(atlas_div_clks),
> +	.gate_clks	= atlas_gate_clks,
> +	.nr_gate_clks	= ARRAY_SIZE(atlas_gate_clks),
> +	.cpu_clks	= atlas_cpu_clks,
> +	.nr_cpu_clks	= ARRAY_SIZE(atlas_cpu_clks),
> +	.nr_clk_ids	= ATLAS_NR_CLK,
> +	.clk_regs	= atlas_clk_regs,
> +	.nr_clk_regs	= ARRAY_SIZE(atlas_clk_regs),
> +};
>   
> -	samsung_clk_of_add_provider(np, ctx);
> +static void __init exynos5433_cmu_atlas_init(struct device_node *np)
> +{
> +	samsung_cmu_register_one(np, &atlas_cmu_info);
>   }
>   CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
>   		exynos5433_cmu_atlas_init);
> 

Looks good to me. Thanks for your work.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
diff mbox series

Patch

diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index f203074d858b..cec66d2a4ee2 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -3675,44 +3675,32 @@  static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst
 	{  0 },
 };
 
+static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = {
+	CPU_CLK(CLK_SCLK_APOLLO, "apolloclk", CLK_MOUT_APOLLO_PLL,
+			CLK_MOUT_BUS_PLL_APOLLO_USER,
+			CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200,
+			exynos5433_apolloclk_d),
+};
+
+static const struct samsung_cmu_info apollo_cmu_info __initconst = {
+	.pll_clks	= apollo_pll_clks,
+	.nr_pll_clks	= ARRAY_SIZE(apollo_pll_clks),
+	.mux_clks	= apollo_mux_clks,
+	.nr_mux_clks	= ARRAY_SIZE(apollo_mux_clks),
+	.div_clks	= apollo_div_clks,
+	.nr_div_clks	= ARRAY_SIZE(apollo_div_clks),
+	.gate_clks	= apollo_gate_clks,
+	.nr_gate_clks	= ARRAY_SIZE(apollo_gate_clks),
+	.cpu_clks	= apollo_cpu_clks,
+	.nr_cpu_clks	= ARRAY_SIZE(apollo_cpu_clks),
+	.nr_clk_ids	= APOLLO_NR_CLK,
+	.clk_regs	= apollo_clk_regs,
+	.nr_clk_regs	= ARRAY_SIZE(apollo_clk_regs),
+};
+
 static void __init exynos5433_cmu_apollo_init(struct device_node *np)
 {
-	void __iomem *reg_base;
-	struct samsung_clk_provider *ctx;
-	struct clk_hw **hws;
-
-	reg_base = of_iomap(np, 0);
-	if (!reg_base) {
-		panic("%s: failed to map registers\n", __func__);
-		return;
-	}
-
-	ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK);
-	if (!ctx) {
-		panic("%s: unable to allocate ctx\n", __func__);
-		return;
-	}
-
-	samsung_clk_register_pll(ctx, apollo_pll_clks,
-				 ARRAY_SIZE(apollo_pll_clks), reg_base);
-	samsung_clk_register_mux(ctx, apollo_mux_clks,
-				 ARRAY_SIZE(apollo_mux_clks));
-	samsung_clk_register_div(ctx, apollo_div_clks,
-				 ARRAY_SIZE(apollo_div_clks));
-	samsung_clk_register_gate(ctx, apollo_gate_clks,
-				  ARRAY_SIZE(apollo_gate_clks));
-
-	hws = ctx->clk_data.hws;
-
-	exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
-		hws[CLK_MOUT_APOLLO_PLL], hws[CLK_MOUT_BUS_PLL_APOLLO_USER], 0x200,
-		exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
-		CLK_CPU_HAS_E5433_REGS_LAYOUT);
-
-	samsung_clk_sleep_init(reg_base, apollo_clk_regs,
-			       ARRAY_SIZE(apollo_clk_regs));
-
-	samsung_clk_of_add_provider(np, ctx);
+	samsung_cmu_register_one(np, &apollo_cmu_info);
 }
 CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
 		exynos5433_cmu_apollo_init);
@@ -3932,44 +3920,32 @@  static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst =
 	{  0 },
 };
 
-static void __init exynos5433_cmu_atlas_init(struct device_node *np)
-{
-	void __iomem *reg_base;
-	struct samsung_clk_provider *ctx;
-	struct clk_hw **hws;
-
-	reg_base = of_iomap(np, 0);
-	if (!reg_base) {
-		panic("%s: failed to map registers\n", __func__);
-		return;
-	}
-
-	ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK);
-	if (!ctx) {
-		panic("%s: unable to allocate ctx\n", __func__);
-		return;
-	}
-
-	samsung_clk_register_pll(ctx, atlas_pll_clks,
-				 ARRAY_SIZE(atlas_pll_clks), reg_base);
-	samsung_clk_register_mux(ctx, atlas_mux_clks,
-				 ARRAY_SIZE(atlas_mux_clks));
-	samsung_clk_register_div(ctx, atlas_div_clks,
-				 ARRAY_SIZE(atlas_div_clks));
-	samsung_clk_register_gate(ctx, atlas_gate_clks,
-				  ARRAY_SIZE(atlas_gate_clks));
-
-	hws = ctx->clk_data.hws;
-
-	exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
-		hws[CLK_MOUT_ATLAS_PLL], hws[CLK_MOUT_BUS_PLL_ATLAS_USER], 0x200,
-		exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
-		CLK_CPU_HAS_E5433_REGS_LAYOUT);
+static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = {
+	CPU_CLK(CLK_SCLK_ATLAS, "atlasclk", CLK_MOUT_ATLAS_PLL,
+			CLK_MOUT_BUS_PLL_ATLAS_USER,
+			CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200,
+			exynos5433_atlasclk_d),
+};
 
-	samsung_clk_sleep_init(reg_base, atlas_clk_regs,
-			       ARRAY_SIZE(atlas_clk_regs));
+static const struct samsung_cmu_info atlas_cmu_info __initconst = {
+	.pll_clks	= atlas_pll_clks,
+	.nr_pll_clks	= ARRAY_SIZE(atlas_pll_clks),
+	.mux_clks	= atlas_mux_clks,
+	.nr_mux_clks	= ARRAY_SIZE(atlas_mux_clks),
+	.div_clks	= atlas_div_clks,
+	.nr_div_clks	= ARRAY_SIZE(atlas_div_clks),
+	.gate_clks	= atlas_gate_clks,
+	.nr_gate_clks	= ARRAY_SIZE(atlas_gate_clks),
+	.cpu_clks	= atlas_cpu_clks,
+	.nr_cpu_clks	= ARRAY_SIZE(atlas_cpu_clks),
+	.nr_clk_ids	= ATLAS_NR_CLK,
+	.clk_regs	= atlas_clk_regs,
+	.nr_clk_regs	= ARRAY_SIZE(atlas_clk_regs),
+};
 
-	samsung_clk_of_add_provider(np, ctx);
+static void __init exynos5433_cmu_atlas_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &atlas_cmu_info);
 }
 CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
 		exynos5433_cmu_atlas_init);