| Message ID | 20211005165408.2305108-3-johan.almbladh@anyfinetworks.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | A new eBPF JIT implementation for MIPS | expand |
在 2021/10/5 17:54, Johan Almbladh 写道: > This patch implements a workaround for the Loongson-2F nop in generated, > code, if the existing option CONFIG_CPU_NOP_WORKAROUND is set. Before, > the binutils option -mfix-loongson2f-nop was enabled, but no workaround > was done when emitting MIPS code. Now, the nop pseudo instruction is > emitted as "or ax,ax,zero" instead of the default "sll zero,zero,0". This > is consistent with the workaround implemented by binutils. > > Link: https://sourceware.org/legacy-ml/binutils/2009-11/msg00387.html > > Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Thanks! - Jiaxun
On Tue, 5 Oct 2021, Johan Almbladh wrote: > This patch implements a workaround for the Loongson-2F nop in generated, > code, if the existing option CONFIG_CPU_NOP_WORKAROUND is set. Before, > the binutils option -mfix-loongson2f-nop was enabled, but no workaround > was done when emitting MIPS code. Now, the nop pseudo instruction is > emitted as "or ax,ax,zero" instead of the default "sll zero,zero,0". This Confusing typo here, s/ax/at/. Maciej
You are right, it should say "at" here instead of "ax". The code uses the MIPS "at" register. AX is a BPF register, so this is a typo in my commit message. Thanks, Johan On Mon, Oct 18, 2021 at 2:00 PM Maciej W. Rozycki <macro@orcam.me.uk> wrote: > > On Tue, 5 Oct 2021, Johan Almbladh wrote: > > > This patch implements a workaround for the Loongson-2F nop in generated, > > code, if the existing option CONFIG_CPU_NOP_WORKAROUND is set. Before, > > the binutils option -mfix-loongson2f-nop was enabled, but no workaround > > was done when emitting MIPS code. Now, the nop pseudo instruction is > > emitted as "or ax,ax,zero" instead of the default "sll zero,zero,0". This > > Confusing typo here, s/ax/at/. > > Maciej
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 5efa4e2dc9ab..296bcf31abb5 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -249,7 +249,11 @@ static inline void uasm_l##lb(struct uasm_label **lab, u32 *addr) \ #define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off) #define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3) #define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b) +#ifdef CONFIG_CPU_NOP_WORKAROUNDS +#define uasm_i_nop(buf) uasm_i_or(buf, 1, 1, 0) +#else #define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0) +#endif #define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1) static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
This patch implements a workaround for the Loongson-2F nop in generated, code, if the existing option CONFIG_CPU_NOP_WORKAROUND is set. Before, the binutils option -mfix-loongson2f-nop was enabled, but no workaround was done when emitting MIPS code. Now, the nop pseudo instruction is emitted as "or ax,ax,zero" instead of the default "sll zero,zero,0". This is consistent with the workaround implemented by binutils. Link: https://sourceware.org/legacy-ml/binutils/2009-11/msg00387.html Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com> --- arch/mips/include/asm/uasm.h | 4 ++++ 1 file changed, 4 insertions(+)