| Message ID | 20210902112520.475901-6-anup.patel@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | QEMU RISC-V AIA support | expand |
On Thu, Sep 2, 2021 at 7:42 PM Anup Patel <anup.patel@wdc.com> wrote: > > The machine or device emulation should be able to force set certain > CPU features because: > 1) We can have certain CPU features which are in-general optional > but implemented by RISC-V CPUs on machine. on the machine > 2) We can have devices which require certain CPU feature. For example, a certain > AIA IMSIC devices expects AIA CSRs implemented by RISC-V CPUs. expect > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > --- > target/riscv/cpu.c | 11 +++-------- > target/riscv/cpu.h | 5 +++++ > 2 files changed, 8 insertions(+), 8 deletions(-) > Otherwise, Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On Thu, Sep 2, 2021 at 9:42 PM Anup Patel <anup.patel@wdc.com> wrote: > > The machine or device emulation should be able to force set certain > CPU features because: > 1) We can have certain CPU features which are in-general optional > but implemented by RISC-V CPUs on machine. > 2) We can have devices which require certain CPU feature. For example, > AIA IMSIC devices expects AIA CSRs implemented by RISC-V CPUs. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 11 +++-------- > target/riscv/cpu.h | 5 +++++ > 2 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 0ade6ad144..9dc9d04923 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -137,11 +137,6 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) > env->vext_ver = vext_ver; > } > > -static void set_feature(CPURISCVState *env, int feature) > -{ > - env->features |= (1ULL << feature); > -} > - > static void set_resetvec(CPURISCVState *env, target_ulong resetvec) > { > #ifndef CONFIG_USER_ONLY > @@ -423,18 +418,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > > if (cpu->cfg.mmu) { > - set_feature(env, RISCV_FEATURE_MMU); > + riscv_set_feature(env, RISCV_FEATURE_MMU); > } > > if (cpu->cfg.pmp) { > - set_feature(env, RISCV_FEATURE_PMP); > + riscv_set_feature(env, RISCV_FEATURE_PMP); > > /* > * Enhanced PMP should only be available > * on harts with PMP support > */ > if (cpu->cfg.epmp) { > - set_feature(env, RISCV_FEATURE_EPMP); > + riscv_set_feature(env, RISCV_FEATURE_EPMP); > } > } > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 59b36f758f..6fe1cc67e5 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -323,6 +323,11 @@ static inline bool riscv_feature(CPURISCVState *env, int feature) > return env->features & (1ULL << feature); > } > > +static inline void riscv_set_feature(CPURISCVState *env, int feature) > +{ > + env->features |= (1ULL << feature); > +} > + > #include "cpu_user.h" > #include "cpu_bits.h" > > -- > 2.25.1 > >
On Sat, Sep 4, 2021 at 8:42 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > On Thu, Sep 2, 2021 at 7:42 PM Anup Patel <anup.patel@wdc.com> wrote: > > > > The machine or device emulation should be able to force set certain > > CPU features because: > > 1) We can have certain CPU features which are in-general optional > > but implemented by RISC-V CPUs on machine. > > on the machine > > > 2) We can have devices which require certain CPU feature. For example, > > a certain > > > AIA IMSIC devices expects AIA CSRs implemented by RISC-V CPUs. > > expect Okay, I will update the commit description based on the above comments. Regards, Anup > > > > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > > --- > > target/riscv/cpu.c | 11 +++-------- > > target/riscv/cpu.h | 5 +++++ > > 2 files changed, 8 insertions(+), 8 deletions(-) > > > > Otherwise, > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0ade6ad144..9dc9d04923 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -137,11 +137,6 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) env->vext_ver = vext_ver; } -static void set_feature(CPURISCVState *env, int feature) -{ - env->features |= (1ULL << feature); -} - static void set_resetvec(CPURISCVState *env, target_ulong resetvec) { #ifndef CONFIG_USER_ONLY @@ -423,18 +418,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } if (cpu->cfg.mmu) { - set_feature(env, RISCV_FEATURE_MMU); + riscv_set_feature(env, RISCV_FEATURE_MMU); } if (cpu->cfg.pmp) { - set_feature(env, RISCV_FEATURE_PMP); + riscv_set_feature(env, RISCV_FEATURE_PMP); /* * Enhanced PMP should only be available * on harts with PMP support */ if (cpu->cfg.epmp) { - set_feature(env, RISCV_FEATURE_EPMP); + riscv_set_feature(env, RISCV_FEATURE_EPMP); } } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 59b36f758f..6fe1cc67e5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -323,6 +323,11 @@ static inline bool riscv_feature(CPURISCVState *env, int feature) return env->features & (1ULL << feature); } +static inline void riscv_set_feature(CPURISCVState *env, int feature) +{ + env->features |= (1ULL << feature); +} + #include "cpu_user.h" #include "cpu_bits.h"
The machine or device emulation should be able to force set certain CPU features because: 1) We can have certain CPU features which are in-general optional but implemented by RISC-V CPUs on machine. 2) We can have devices which require certain CPU feature. For example, AIA IMSIC devices expects AIA CSRs implemented by RISC-V CPUs. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- target/riscv/cpu.c | 11 +++-------- target/riscv/cpu.h | 5 +++++ 2 files changed, 8 insertions(+), 8 deletions(-)