diff mbox series

[01/11] drm/msm/dpu: move LUT levels out of QOS config

Message ID 20210930140002.308628-2-dmitry.baryshkov@linaro.org (mailing list archive)
State Not Applicable
Headers show
Series drm/msm/dpu: cleanup plane state | expand

Commit Message

Dmitry Baryshkov Sept. 30, 2021, 1:59 p.m. UTC 
LUT levels are setup outside of setup_qos_ctrl, so remove them from the
struct dpu_hw_pipe_qos_cfg.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 15 ++++++++-------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 16 ++++++----------
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   | 17 ++++++-----------
 3 files changed, 20 insertions(+), 28 deletions(-)

Comments

Abhinav Kumar Oct. 21, 2021, 10:22 p.m. UTC | #1 
On 2021-09-30 06:59, Dmitry Baryshkov wrote:
> LUT levels are setup outside of setup_qos_ctrl, so remove them from the
> struct dpu_hw_pipe_qos_cfg.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 15 ++++++++-------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 16 ++++++----------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   | 17 ++++++-----------
>  3 files changed, 20 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 69eed7932486..cbafb61404d0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -569,19 +569,20 @@ static void dpu_hw_sspp_setup_solidfill(struct
> dpu_hw_pipe *ctx, u32 color, enum
>  }
> 
>  static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
> -		struct dpu_hw_pipe_qos_cfg *cfg)
> +			u32 danger_lut,
> +			u32 safe_lut)
>  {
>  	u32 idx;
> 
>  	if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
>  		return;
> 
> -	DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, cfg->danger_lut);
> -	DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, cfg->safe_lut);
> +	DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, danger_lut);
> +	DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut);
>  }
> 
>  static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
> -		struct dpu_hw_pipe_qos_cfg *cfg)
> +			u64 creq_lut)
>  {
>  	u32 idx;
> 
> @@ -589,11 +590,11 @@ static void dpu_hw_sspp_setup_creq_lut(struct
> dpu_hw_pipe *ctx,
>  		return;
> 
>  	if (ctx->cap && test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features)) {
> -		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, cfg->creq_lut);
> +		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, creq_lut);
>  		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx,
> -				cfg->creq_lut >> 32);
> +				creq_lut >> 32);
>  	} else {
> -		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, cfg->creq_lut);
> +		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, creq_lut);
>  	}
>  }
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index fdfd4b46e2c6..27263bc1a1ef 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -166,18 +166,12 @@ struct dpu_hw_pipe_cfg {
> 
>  /**
>   * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration
> - * @danger_lut: LUT for generate danger level based on fill level
> - * @safe_lut: LUT for generate safe level based on fill level
> - * @creq_lut: LUT for generate creq level based on fill level
>   * @creq_vblank: creq value generated to vbif during vertical blanking
>   * @danger_vblank: danger value generated during vertical blanking
>   * @vblank_en: enable creq_vblank and danger_vblank during vblank
>   * @danger_safe_en: enable danger safe generation
>   */
>  struct dpu_hw_pipe_qos_cfg {
> -	u32 danger_lut;
> -	u32 safe_lut;
> -	u64 creq_lut;
>  	u32 creq_vblank;
>  	u32 danger_vblank;
>  	bool vblank_en;
> @@ -302,20 +296,22 @@ struct dpu_hw_sspp_ops {
>  	/**
>  	 * setup_danger_safe_lut - setup danger safe LUTs
>  	 * @ctx: Pointer to pipe context
> -	 * @cfg: Pointer to pipe QoS configuration
> +	 * @danger_lut: LUT for generate danger level based on fill level
> +	 * @safe_lut: LUT for generate safe level based on fill level
>  	 *
>  	 */
>  	void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx,
> -			struct dpu_hw_pipe_qos_cfg *cfg);
> +			u32 danger_lut,
> +			u32 safe_lut);
> 
>  	/**
>  	 * setup_creq_lut - setup CREQ LUT
>  	 * @ctx: Pointer to pipe context
> -	 * @cfg: Pointer to pipe QoS configuration
> +	 * @creq_lut: LUT for generate creq level based on fill level
>  	 *
>  	 */
>  	void (*setup_creq_lut)(struct dpu_hw_pipe *ctx,
> -			struct dpu_hw_pipe_qos_cfg *cfg);
> +			u64 creq_lut);
> 
>  	/**
>  	 * setup_qos_ctrl - setup QoS control
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index c989621209aa..5e0d06f26e53 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -348,8 +348,6 @@ static void _dpu_plane_set_qos_lut(struct drm_plane 
> *plane,
>  	qos_lut = _dpu_plane_get_qos_lut(
>  			&pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl);
> 
> -	pdpu->pipe_qos_cfg.creq_lut = qos_lut;
> -
>  	trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
>  			(fmt) ? fmt->base.pixel_format : 0,
>  			pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
> @@ -359,7 +357,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane 
> *plane,
>  			fmt ? (char *)&fmt->base.pixel_format : NULL,
>  			pdpu->is_rt_pipe, total_fl, qos_lut);
> 
> -	pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, 
> &pdpu->pipe_qos_cfg);
> +	pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut);
>  }
> 
>  /**
> @@ -397,24 +395,21 @@ static void _dpu_plane_set_danger_lut(struct
> drm_plane *plane,
>  		}
>  	}
> 
> -	pdpu->pipe_qos_cfg.danger_lut = danger_lut;
> -	pdpu->pipe_qos_cfg.safe_lut = safe_lut;
> -
>  	trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
>  			(fmt) ? fmt->base.pixel_format : 0,
>  			(fmt) ? fmt->fetch_mode : 0,
> -			pdpu->pipe_qos_cfg.danger_lut,
> -			pdpu->pipe_qos_cfg.safe_lut);
> +			danger_lut,
> +			safe_lut);
> 
>  	DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 
> 0x%x]\n",
>  		pdpu->pipe - SSPP_VIG0,
>  		fmt ? (char *)&fmt->base.pixel_format : NULL,
>  		fmt ? fmt->fetch_mode : -1,
> -		pdpu->pipe_qos_cfg.danger_lut,
> -		pdpu->pipe_qos_cfg.safe_lut);
> +		danger_lut,
> +		safe_lut);
> 
>  	pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
> -			&pdpu->pipe_qos_cfg);
> +			danger_lut, safe_lut);
>  }
> 
>  /**
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 69eed7932486..cbafb61404d0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -569,19 +569,20 @@  static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum
 }
 
 static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
-		struct dpu_hw_pipe_qos_cfg *cfg)
+			u32 danger_lut,
+			u32 safe_lut)
 {
 	u32 idx;
 
 	if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
 		return;
 
-	DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, cfg->danger_lut);
-	DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, cfg->safe_lut);
+	DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, danger_lut);
+	DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut);
 }
 
 static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
-		struct dpu_hw_pipe_qos_cfg *cfg)
+			u64 creq_lut)
 {
 	u32 idx;
 
@@ -589,11 +590,11 @@  static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
 		return;
 
 	if (ctx->cap && test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features)) {
-		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, cfg->creq_lut);
+		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, creq_lut);
 		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx,
-				cfg->creq_lut >> 32);
+				creq_lut >> 32);
 	} else {
-		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, cfg->creq_lut);
+		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, creq_lut);
 	}
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index fdfd4b46e2c6..27263bc1a1ef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -166,18 +166,12 @@  struct dpu_hw_pipe_cfg {
 
 /**
  * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration
- * @danger_lut: LUT for generate danger level based on fill level
- * @safe_lut: LUT for generate safe level based on fill level
- * @creq_lut: LUT for generate creq level based on fill level
  * @creq_vblank: creq value generated to vbif during vertical blanking
  * @danger_vblank: danger value generated during vertical blanking
  * @vblank_en: enable creq_vblank and danger_vblank during vblank
  * @danger_safe_en: enable danger safe generation
  */
 struct dpu_hw_pipe_qos_cfg {
-	u32 danger_lut;
-	u32 safe_lut;
-	u64 creq_lut;
 	u32 creq_vblank;
 	u32 danger_vblank;
 	bool vblank_en;
@@ -302,20 +296,22 @@  struct dpu_hw_sspp_ops {
 	/**
 	 * setup_danger_safe_lut - setup danger safe LUTs
 	 * @ctx: Pointer to pipe context
-	 * @cfg: Pointer to pipe QoS configuration
+	 * @danger_lut: LUT for generate danger level based on fill level
+	 * @safe_lut: LUT for generate safe level based on fill level
 	 *
 	 */
 	void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx,
-			struct dpu_hw_pipe_qos_cfg *cfg);
+			u32 danger_lut,
+			u32 safe_lut);
 
 	/**
 	 * setup_creq_lut - setup CREQ LUT
 	 * @ctx: Pointer to pipe context
-	 * @cfg: Pointer to pipe QoS configuration
+	 * @creq_lut: LUT for generate creq level based on fill level
 	 *
 	 */
 	void (*setup_creq_lut)(struct dpu_hw_pipe *ctx,
-			struct dpu_hw_pipe_qos_cfg *cfg);
+			u64 creq_lut);
 
 	/**
 	 * setup_qos_ctrl - setup QoS control
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index c989621209aa..5e0d06f26e53 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -348,8 +348,6 @@  static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
 	qos_lut = _dpu_plane_get_qos_lut(
 			&pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl);
 
-	pdpu->pipe_qos_cfg.creq_lut = qos_lut;
-
 	trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
 			(fmt) ? fmt->base.pixel_format : 0,
 			pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
@@ -359,7 +357,7 @@  static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
 			fmt ? (char *)&fmt->base.pixel_format : NULL,
 			pdpu->is_rt_pipe, total_fl, qos_lut);
 
-	pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, &pdpu->pipe_qos_cfg);
+	pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut);
 }
 
 /**
@@ -397,24 +395,21 @@  static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
 		}
 	}
 
-	pdpu->pipe_qos_cfg.danger_lut = danger_lut;
-	pdpu->pipe_qos_cfg.safe_lut = safe_lut;
-
 	trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
 			(fmt) ? fmt->base.pixel_format : 0,
 			(fmt) ? fmt->fetch_mode : 0,
-			pdpu->pipe_qos_cfg.danger_lut,
-			pdpu->pipe_qos_cfg.safe_lut);
+			danger_lut,
+			safe_lut);
 
 	DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
 		pdpu->pipe - SSPP_VIG0,
 		fmt ? (char *)&fmt->base.pixel_format : NULL,
 		fmt ? fmt->fetch_mode : -1,
-		pdpu->pipe_qos_cfg.danger_lut,
-		pdpu->pipe_qos_cfg.safe_lut);
+		danger_lut,
+		safe_lut);
 
 	pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
-			&pdpu->pipe_qos_cfg);
+			danger_lut, safe_lut);
 }
 
 /**