diff mbox series

[10/11] drm/msm/dpu: don't cache pipe->cap->sblk in dpu_plane

Message ID 20210930140002.308628-11-dmitry.baryshkov@linaro.org (mailing list archive)
State Not Applicable
Headers show
Series drm/msm/dpu: cleanup plane state | expand

Commit Message

Dmitry Baryshkov Sept. 30, 2021, 2 p.m. UTC
Do not cache hw_pipe's sblk in dpu_plane. Use
pdpu->pipe_hw->cap->sblk directly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 25 ++++++++---------------
 1 file changed, 8 insertions(+), 17 deletions(-)

Comments

Abhinav Kumar Oct. 21, 2021, 11:29 p.m. UTC | #1
On 2021-09-30 07:00, Dmitry Baryshkov wrote:
> Do not cache hw_pipe's sblk in dpu_plane. Use
> pdpu->pipe_hw->cap->sblk directly.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 25 ++++++++---------------
>  1 file changed, 8 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index af403c0d3d7d..d8018e664925 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -109,8 +109,6 @@ struct dpu_plane {
>  	struct list_head mplane_list;
>  	struct dpu_mdss_cfg *catalog;
> 
> -	const struct dpu_sspp_sub_blks *pipe_sblk;
> -
>  	/* debugfs related stuff */
>  	struct dentry *debugfs_root;
>  	struct dpu_debugfs_regset32 debugfs_src;
> @@ -425,9 +423,9 @@ static void _dpu_plane_set_qos_ctrl(struct 
> drm_plane *plane,
>  	memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
> 
>  	if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
> -		pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank;
> +		pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank;
>  		pipe_qos_cfg.danger_vblank =
> -				pdpu->pipe_sblk->danger_vblank;
> +				pdpu->pipe_hw->cap->sblk->danger_vblank;
>  		pipe_qos_cfg.vblank_en = enable;
>  	}
> 
> @@ -982,10 +980,10 @@ static int dpu_plane_atomic_check(struct 
> drm_plane *plane,
>  		crtc_state = drm_atomic_get_new_crtc_state(state,
>  							   new_plane_state->crtc);
> 
> -	min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxupscale);
> +	min_scale = FRAC_16_16(1, pdpu->pipe_hw->cap->sblk->maxupscale);
>  	ret = drm_atomic_helper_check_plane_state(new_plane_state, 
> crtc_state,
>  						  min_scale,
> -						  pdpu->pipe_sblk->maxdwnscale << 16,
> +						  pdpu->pipe_hw->cap->sblk->maxdwnscale << 16,
>  						  true, true);
>  	if (ret) {
>  		DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
> @@ -1611,20 +1609,13 @@ struct drm_plane *dpu_plane_init(struct 
> drm_device *dev,
>  		goto clean_sspp;
>  	}
> 
> -	/* cache features mask for later */
> -	pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk;
> -	if (!pdpu->pipe_sblk) {
> -		DPU_ERROR("[%u]invalid sblk\n", pipe);
> -		goto clean_sspp;
> -	}
> -
>  	if (pdpu->is_virtual) {
> -		format_list = pdpu->pipe_sblk->virt_format_list;
> -		num_formats = pdpu->pipe_sblk->virt_num_formats;
> +		format_list = pdpu->pipe_hw->cap->sblk->virt_format_list;
> +		num_formats = pdpu->pipe_hw->cap->sblk->virt_num_formats;
>  	}
>  	else {
> -		format_list = pdpu->pipe_sblk->format_list;
> -		num_formats = pdpu->pipe_sblk->num_formats;
> +		format_list = pdpu->pipe_hw->cap->sblk->format_list;
> +		num_formats = pdpu->pipe_hw->cap->sblk->num_formats;
>  	}
> 
>  	ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index af403c0d3d7d..d8018e664925 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -109,8 +109,6 @@  struct dpu_plane {
 	struct list_head mplane_list;
 	struct dpu_mdss_cfg *catalog;
 
-	const struct dpu_sspp_sub_blks *pipe_sblk;
-
 	/* debugfs related stuff */
 	struct dentry *debugfs_root;
 	struct dpu_debugfs_regset32 debugfs_src;
@@ -425,9 +423,9 @@  static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
 	memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
 
 	if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
-		pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank;
+		pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank;
 		pipe_qos_cfg.danger_vblank =
-				pdpu->pipe_sblk->danger_vblank;
+				pdpu->pipe_hw->cap->sblk->danger_vblank;
 		pipe_qos_cfg.vblank_en = enable;
 	}
 
@@ -982,10 +980,10 @@  static int dpu_plane_atomic_check(struct drm_plane *plane,
 		crtc_state = drm_atomic_get_new_crtc_state(state,
 							   new_plane_state->crtc);
 
-	min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxupscale);
+	min_scale = FRAC_16_16(1, pdpu->pipe_hw->cap->sblk->maxupscale);
 	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
 						  min_scale,
-						  pdpu->pipe_sblk->maxdwnscale << 16,
+						  pdpu->pipe_hw->cap->sblk->maxdwnscale << 16,
 						  true, true);
 	if (ret) {
 		DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
@@ -1611,20 +1609,13 @@  struct drm_plane *dpu_plane_init(struct drm_device *dev,
 		goto clean_sspp;
 	}
 
-	/* cache features mask for later */
-	pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk;
-	if (!pdpu->pipe_sblk) {
-		DPU_ERROR("[%u]invalid sblk\n", pipe);
-		goto clean_sspp;
-	}
-
 	if (pdpu->is_virtual) {
-		format_list = pdpu->pipe_sblk->virt_format_list;
-		num_formats = pdpu->pipe_sblk->virt_num_formats;
+		format_list = pdpu->pipe_hw->cap->sblk->virt_format_list;
+		num_formats = pdpu->pipe_hw->cap->sblk->virt_num_formats;
 	}
 	else {
-		format_list = pdpu->pipe_sblk->format_list;
-		num_formats = pdpu->pipe_sblk->num_formats;
+		format_list = pdpu->pipe_hw->cap->sblk->format_list;
+		num_formats = pdpu->pipe_hw->cap->sblk->num_formats;
 	}
 
 	ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,