| Message ID | 20211021194547.672988-1-matheus.ferst@eldorado.org.br (mailing list archive) |
|---|---|
| Headers | show |
| Series | PowerISA v3.1 instruction batch | expand |
On 10/21/21 12:45 PM, matheus.ferst@eldorado.org.br wrote: > From: Matheus Ferst<matheus.ferst@eldorado.org.br> > > This patch series implements 56 new instructions for POWER10, moving 28 > "old" instructions to decodetree along the way. The series is divided by > facility as follows: > > - From patch 1 to 4: Floating-Point > - From patch 5 to 10: Fixed-Point > - From patch 11 to 19: Vector > - From patch 20 to 33: Vector-Scalar Extensions > > Based-on:<20210910112624.72748-1-luis.pires@eldorado.org.br> > because of patch 10 ("target/ppc: Move REQUIRE_ALTIVEC/VECTOR to > translate.c") and patch 11 ("target/ppc: Introduce REQUIRE_FPU"). The prereqs no longer apply cleanly. Do you have a branch you can publish in the meantime? r~
On 21/10/2021 23:06, Richard Henderson wrote: > [E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você > possa confirmar o remetente e saber que o conteúdo é seguro. Em caso de > e-mail suspeito entre imediatamente em contato com o DTI. > > On 10/21/21 12:45 PM, matheus.ferst@eldorado.org.br wrote: >> From: Matheus Ferst<matheus.ferst@eldorado.org.br> >> >> This patch series implements 56 new instructions for POWER10, moving 28 >> "old" instructions to decodetree along the way. The series is divided by >> facility as follows: >> >> - From patch 1 to 4: Floating-Point >> - From patch 5 to 10: Fixed-Point >> - From patch 11 to 19: Vector >> - From patch 20 to 33: Vector-Scalar Extensions >> >> Based-on:<20210910112624.72748-1-luis.pires@eldorado.org.br> >> because of patch 10 ("target/ppc: Move REQUIRE_ALTIVEC/VECTOR to >> translate.c") and patch 11 ("target/ppc: Introduce REQUIRE_FPU"). > > The prereqs no longer apply cleanly. Do you have a branch you can > publish in the meantime? > > > r~ I forgot to mention that it's also based on Gibson's ppc-for-6.2. The branch is available on https://github.com/PPC64/qemu/tree/ppc-isa31-review Thanks, Matheus K. Ferst Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/> Analista de Software Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
From: Matheus Ferst <matheus.ferst@eldorado.org.br> This patch series implements 56 new instructions for POWER10, moving 28 "old" instructions to decodetree along the way. The series is divided by facility as follows: - From patch 1 to 4: Floating-Point - From patch 5 to 10: Fixed-Point - From patch 11 to 19: Vector - From patch 20 to 33: Vector-Scalar Extensions Based-on: <20210910112624.72748-1-luis.pires@eldorado.org.br> because of patch 10 ("target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c") and patch 11 ("target/ppc: Introduce REQUIRE_FPU"). Bruno Larsen (billionai) (6): target/ppc: Introduce REQUIRE_VSX macro target/ppc: moved XXSPLTW to using decodetree target/ppc: moved XXSPLTIB to using decodetree target/ppc: implemented XXSPLTI32DX target/ppc: Implemented XXSPLTIW using decodetree target/ppc: implemented XXSPLTIDP instruction Lucas Mateus Castro (alqotel) (6): target/ppc: moved stxv and lxv from legacy to decodtree target/ppc: moved stxvx and lxvx from legacy to decodtree target/ppc: added the instructions LXVP and STXVP target/ppc: added the instructions LXVPX and STXVPX target/ppc: added the instructions PLXV and PSTXV target/ppc: added the instructions PLXVP and PSTXVP Luis Pires (2): target/ppc: Implement cntlzdm target/ppc: Implement cnttzdm Matheus Ferst (15): target/ppc: Move LQ and STQ to decodetree target/ppc: Implement PLQ and PSTQ target/ppc: Implement pdepd instruction target/ppc: Implement pextd instruction target/ppc: Move vcfuged to vmx-impl.c.inc target/ppc: Implement vclzdm/vctzdm instructions target/ppc: Implement vpdepd/vpextd instruction target/ppc: Implement vsldbi/vsrdbi instructions target/ppc: Implement Vector Insert from GPR using GPR index insns target/ppc: Implement Vector Insert Word from GPR using Immediate insns target/ppc: Implement Vector Insert from VSR using GPR index insns target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree target/ppc: Implement Vector Extract Double to VSR using GPR index insns target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions target/ppc: Implement lxvkq instruction pherde (4): target/ppc: introduce do_ea_calc target/ppc: move resolve_PLS_D to translate.c target/ppc: Move load and store floating point instructions to decodetree target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions target/ppc/helper.h | 22 +- target/ppc/insn32.decode | 132 +++++++ target/ppc/insn64.decode | 72 ++++ target/ppc/int_helper.c | 169 +++++++- target/ppc/translate.c | 213 +++-------- target/ppc/translate/fixedpoint-impl.c.inc | 188 +++++++-- target/ppc/translate/fp-impl.c.inc | 254 ++++-------- target/ppc/translate/fp-ops.c.inc | 29 -- target/ppc/translate/vector-impl.c.inc | 48 --- target/ppc/translate/vmx-impl.c.inc | 358 ++++++++++++++++- target/ppc/translate/vmx-ops.c.inc | 10 +- target/ppc/translate/vsx-impl.c.inc | 424 ++++++++++++++------- target/ppc/translate/vsx-ops.c.inc | 4 - 13 files changed, 1298 insertions(+), 625 deletions(-) delete mode 100644 target/ppc/translate/vector-impl.c.inc