diff mbox series

[21/33] target/ppc: moved stxv and lxv from legacy to decodtree

Message ID 20211021194547.672988-22-matheus.ferst@eldorado.org.br (mailing list archive)
State New, archived
Headers show
Series PowerISA v3.1 instruction batch | expand

Commit Message

Matheus K. Ferst Oct. 21, 2021, 7:45 p.m. UTC 
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>

Moved stxv and lxv implementation from the legacy system to
decodetree.

Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/insn32.decode            |  8 ++++
 target/ppc/translate.c              | 17 +-------
 target/ppc/translate/vsx-impl.c.inc | 60 ++++++++++++++++++++++++++++-
 3 files changed, 68 insertions(+), 17 deletions(-)

Comments

Richard Henderson Oct. 23, 2021, 8:34 p.m. UTC | #1 
On 10/21/21 12:45 PM, matheus.ferst@eldorado.org.br wrote:
> +static bool do_lstxv(DisasContext *ctx, int ra, int displ,
> +                     int rt, bool store)

You need an int64_t displ before you add PLXV et al.  What happened to passing in arg_D as 
for the other integer instructions?

> +    do_ea_calc(ctx, ra, tcg_const_tl(displ), ea);
> +
> +    if (ctx->le_mode) {
> +        gen_addr_add(ctx, ea, ea, 8);
> +        offset = -8;
> +    } else {
> +        offset = 8;
> +    }

Adjust displ for le_mode, then you don't have to do the addition twice.


r~
Richard Henderson Oct. 23, 2021, 8:39 p.m. UTC | #2 
On 10/23/21 1:34 PM, Richard Henderson wrote:
> On 10/21/21 12:45 PM, matheus.ferst@eldorado.org.br wrote:
>> +static bool do_lstxv(DisasContext *ctx, int ra, int displ,
>> +                     int rt, bool store)
> 
> You need an int64_t displ before you add PLXV et al.  What happened to passing in arg_D as 
> for the other integer instructions?
> 
>> +    do_ea_calc(ctx, ra, tcg_const_tl(displ), ea);
>> +
>> +    if (ctx->le_mode) {
>> +        gen_addr_add(ctx, ea, ea, 8);
>> +        offset = -8;
>> +    } else {
>> +        offset = 8;
>> +    }
> 
> Adjust displ for le_mode, then you don't have to do the addition twice.

Nevermind, next patch fixes this one.
Fold the 3 lines back for a

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
Richard Henderson Oct. 23, 2021, 8:46 p.m. UTC | #3 
On 10/21/21 12:45 PM, matheus.ferst@eldorado.org.br wrote:
> +    if (ctx->le_mode) {
> +        gen_addr_add(ctx, ea, ea, 8);
> +        offset = -8;
> +    } else {
> +        offset = 8;
> +    }
> +
> +    if (store) {
> +        get_cpu_vsrh(xt, rt);
> +        tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
> +        gen_addr_add(ctx, ea, ea, offset);
> +        get_cpu_vsrl(xt, rt);
> +        tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
> +    } else {
> +        tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
> +        set_cpu_vsrh(rt, xt);
> +        gen_addr_add(ctx, ea, ea, offset);
> +        tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
> +        set_cpu_vsrl(rt, xt);
> +    }

Actually, I'm going to reverse myself again.

This has a behaviour change: for LE, the first access is to EA+8 instead of EA.  Thus the 
SIGSEGV for a load from NULL will report address 8 not 0, which is probably not the 
correct result.


r~
diff mbox series

Patch

diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e438177b32..296d6d6c5a 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -28,6 +28,9 @@ 
 %dq_rtp         22:4   !function=times_2
 @DQ_rtp         ...... ....0 ra:5 ............ ....             &D rt=%dq_rtp si=%dq_si
 
+%dq_rt_tsx      3:1 21:5
+@DQ_TSX         ...... ..... ra:5 ............ ....             &D si=%dq_si rt=%dq_rt_tsx
+
 %ds_si          2:s14  !function=times_4
 @DS             ...... rt:5 ra:5 .............. ..      &D si=%ds_si
 
@@ -385,3 +388,8 @@  VINSWVRX        000100 ..... ..... ..... 00110001111    @VX
 
 VSLDBI          000100 ..... ..... ..... 00 ... 010110  @VN
 VSRDBI          000100 ..... ..... ..... 01 ... 010110  @VN
+
+# VSX Load/Store Instructions
+
+LXV             111101 ..... ..... ............ . 001   @DQ_TSX
+STXV            111101 ..... ..... ............ . 101   @DQ_TSX
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d11029d03a..f109830207 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7444,20 +7444,7 @@  static void gen_dform39(DisasContext *ctx)
 /* handles stfdp, lxv, stxsd, stxssp lxvx */
 static void gen_dform3D(DisasContext *ctx)
 {
-    if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
-        switch (ctx->opcode & 0x7) {
-        case 1: /* lxv */
-            if (ctx->insns_flags2 & PPC2_ISA300) {
-                return gen_lxv(ctx);
-            }
-            break;
-        case 5: /* stxv */
-            if (ctx->insns_flags2 & PPC2_ISA300) {
-                return gen_stxv(ctx);
-            }
-            break;
-        }
-    } else { /* DS-FORM */
+    if ((ctx->opcode & 3) != 1) { /* DS-FORM */
         switch (ctx->opcode & 0x3) {
         case 0: /* stfdp */
             if (ctx->insns_flags2 & PPC2_ISA205) {
@@ -7582,7 +7569,7 @@  GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
 #endif
 /* handles lfdp, lxsd, lxssp */
 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
-/* handles stfdp, lxv, stxsd, stxssp, stxv */
+/* handles stfdp, stxsd, stxssp */
 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 57a7f73bba..dd14be6ee5 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -317,7 +317,6 @@  static void gen_##name(DisasContext *ctx)                   \
     tcg_temp_free_i64(xtl);                                 \
 }
 
-VSX_VECTOR_LOAD(lxv, ld_i64, 0)
 VSX_VECTOR_LOAD(lxvx, ld_i64, 1)
 
 #define VSX_VECTOR_STORE(name, op, indexed)                 \
@@ -370,7 +369,6 @@  static void gen_##name(DisasContext *ctx)                   \
     tcg_temp_free_i64(xtl);                                 \
 }
 
-VSX_VECTOR_STORE(stxv, st_i64, 0)
 VSX_VECTOR_STORE(stxvx, st_i64, 1)
 
 #ifdef TARGET_PPC64
@@ -2077,6 +2075,64 @@  static void gen_xvxsigdp(DisasContext *ctx)
     tcg_temp_free_i64(xbl);
 }
 
+static bool do_lstxv(DisasContext *ctx, int ra, int displ,
+                     int rt, bool store)
+{
+    TCGv ea;
+    TCGv_i64 xt;
+    MemOp mop;
+    int offset;
+
+    ea = tcg_temp_new();
+    xt = tcg_temp_new_i64();
+
+    mop = DEF_MEMOP(MO_Q);
+
+    gen_set_access_type(ctx, ACCESS_INT);
+    do_ea_calc(ctx, ra, tcg_const_tl(displ), ea);
+
+    if (ctx->le_mode) {
+        gen_addr_add(ctx, ea, ea, 8);
+        offset = -8;
+    } else {
+        offset = 8;
+    }
+
+    if (store) {
+        get_cpu_vsrh(xt, rt);
+        tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+        gen_addr_add(ctx, ea, ea, offset);
+        get_cpu_vsrl(xt, rt);
+        tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+    } else {
+        tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+        set_cpu_vsrh(rt, xt);
+        gen_addr_add(ctx, ea, ea, offset);
+        tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+        set_cpu_vsrl(rt, xt);
+    }
+
+    tcg_temp_free(ea);
+    tcg_temp_free_i64(xt);
+    return true;
+}
+
+static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store)
+{
+    REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+
+    if (a->rt >= 32) {
+        REQUIRE_VSX(ctx);
+    } else {
+        REQUIRE_VECTOR(ctx);
+    }
+
+    return do_lstxv(ctx, a->ra, a->si, a->rt, store);
+}
+
+TRANS(STXV, do_lstxv_D, true)
+TRANS(LXV, do_lstxv_D, false)
+
 #undef GEN_XX2FORM
 #undef GEN_XX3FORM
 #undef GEN_XX2IFORM