diff mbox series

[24/33] target/ppc: added the instructions LXVPX and STXVPX

Message ID 20211021194547.672988-25-matheus.ferst@eldorado.org.br (mailing list archive)
State New, archived
Headers show
Series PowerISA v3.1 instruction batch | expand

Commit Message

Matheus K. Ferst Oct. 21, 2021, 7:45 p.m. UTC 
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>

Implemented the instructions lxvpx and stxvpx using decodetree

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/insn32.decode            |  3 +++
 target/ppc/translate/vsx-impl.c.inc | 18 ++++++++++++------
 2 files changed, 15 insertions(+), 6 deletions(-)

Comments

Richard Henderson Oct. 23, 2021, 8:49 p.m. UTC | #1 
On 10/21/21 12:45 PM, matheus.ferst@eldorado.org.br wrote:
> From: "Lucas Mateus Castro (alqotel)"<lucas.castro@eldorado.org.br>
> 
> Implemented the instructions lxvpx and stxvpx using decodetree
> 
> Signed-off-by: Lucas Mateus Castro (alqotel)<lucas.castro@eldorado.org.br>
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
>   target/ppc/insn32.decode            |  3 +++
>   target/ppc/translate/vsx-impl.c.inc | 18 ++++++++++++------
>   2 files changed, 15 insertions(+), 6 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index c252dec02f..e4508631b0 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -108,6 +108,7 @@ 
 
 %x_rt_tsx       0:1 21:5
 @X_TSX          ...... ..... ra:5 rb:5 .......... .             &X rt=%x_rt_tsx
+@X_TSXP         ...... ..... ra:5 rb:5 .......... .             &X rt=%rt_tsxp
 
 &X_frtp_vrb     frtp vrb
 @X_frtp_vrb     ...... ....0 ..... vrb:5 .......... .           &X_frtp_vrb frtp=%x_frtp
@@ -403,3 +404,5 @@  LXVP            000110 ..... ..... ............ 0000    @DQ_TSXP
 STXVP           000110 ..... ..... ............ 0001    @DQ_TSXP
 LXVX            011111 ..... ..... ..... 0100 - 01100 . @X_TSX
 STXVX           011111 ..... ..... ..... 0110001100 .   @X_TSX
+LXVPX           011111 ..... ..... ..... 0101001101 -   @X_TSXP
+STXVPX          011111 ..... ..... ..... 0111001101 -   @X_TSXP
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 46dd5a1bea..d3e2e4ff8e 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2044,25 +2044,31 @@  static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store, bool paired)
     return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store, paired);
 }
 
-static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store)
+static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
 {
-    REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+    if (paired) {
+        REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+    } else {
+        REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+    }
 
-    if (a->rt >= 32) {
+    if (paired || a->rt >= 32) {
         REQUIRE_VSX(ctx);
     } else {
         REQUIRE_VECTOR(ctx);
     }
 
-    return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, false);
+    return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, paired);
 }
 
 TRANS(STXV, do_lstxv_D, true, false)
 TRANS(LXV, do_lstxv_D, false, false)
 TRANS(STXVP, do_lstxv_D, true, true)
 TRANS(LXVP, do_lstxv_D, false, true)
-TRANS(STXVX, do_lstxv_X, true)
-TRANS(LXVX, do_lstxv_X, false)
+TRANS(STXVX, do_lstxv_X, true, false)
+TRANS(LXVX, do_lstxv_X, false, false)
+TRANS(STXVPX, do_lstxv_X, true, true)
+TRANS(LXVPX, do_lstxv_X, false, true)
 
 #undef GEN_XX2FORM
 #undef GEN_XX3FORM