| Message ID | 1635135575-5668-1-git-send-email-quic_c_sanm@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [v2] phy: qcom-snps: Correct the FSEL_MASK | expand |
On 25-10-21, 09:49, Sandeep Maheswaram wrote: > The FSEL_MASK which selects the refclock is defined incorrectly. > It should be [4:6] not [5:7]. Due to this incorrect definition, the BIT(7) > in USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 is reset which keeps PHY analog > blocks ON during suspend. > Fix this issue by correctly defining the FSEL_MASK. Applied, thanks
On 25-10-21, 09:49, Sandeep Maheswaram wrote: > The FSEL_MASK which selects the refclock is defined incorrectly. > It should be [4:6] not [5:7]. Due to this incorrect definition, the BIT(7) > in USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 is reset which keeps PHY analog > blocks ON during suspend. > Fix this issue by correctly defining the FSEL_MASK. > > Fixes: 51e8114f80d0 (phy: qcom-snps: Add SNPS USB PHY driver for > QCOM based SOCs) 1. pls never split the fixes line! 2. Format is Fixes: 51e8114f80d0 ("phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs") Pls dont use your own format I have fixed it up while applying... > Signed-off-by: Sandeep Maheswaram <quic_c_sanm@quicinc.com> > --- > v2: > Corrected the register name COMMON1 > COMMMON0 in commit description. > Added Fixes tag. > Dropped copyright line. > > drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c > index ae4bac0..7e61202 100644 > --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c > +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c > @@ -33,7 +33,7 @@ > > #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) > #define RETENABLEN BIT(3) > -#define FSEL_MASK GENMASK(7, 5) > +#define FSEL_MASK GENMASK(6, 4) > #define FSEL_DEFAULT (0x3 << 4) > > #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58) > -- > 2.7.4
diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c index ae4bac0..7e61202 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -33,7 +33,7 @@ #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) #define RETENABLEN BIT(3) -#define FSEL_MASK GENMASK(7, 5) +#define FSEL_MASK GENMASK(6, 4) #define FSEL_DEFAULT (0x3 << 4) #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58)
The FSEL_MASK which selects the refclock is defined incorrectly. It should be [4:6] not [5:7]. Due to this incorrect definition, the BIT(7) in USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 is reset which keeps PHY analog blocks ON during suspend. Fix this issue by correctly defining the FSEL_MASK. Fixes: 51e8114f80d0 (phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs) Signed-off-by: Sandeep Maheswaram <quic_c_sanm@quicinc.com> --- v2: Corrected the register name COMMON1 > COMMMON0 in commit description. Added Fixes tag. Dropped copyright line. drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)