| Message ID | 1635152851-23660-4-git-send-email-quic_c_sanm@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | USB DWC3 QCOM Multi power domain support | expand |
Quoting Sandeep Maheswaram (2021-10-25 02:07:31) > Add multi pd support to set performance state for cx domain > to maintain minimum corner voltage for USB clocks. > > Signed-off-by: Sandeep Maheswaram <quic_c_sanm@quicinc.com> > --- > v2: > Changed rpmhd_opp_svs to rmphd_opp_nom for cx domain. > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index d74a4c8..9e3b6ad 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -2538,7 +2538,8 @@ > interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", > "dm_hs_phy_irq", "ss_phy_irq"; > > - power-domains = <&gcc GCC_USB30_PRIM_GDSC>; > + power-domains = <&rpmhpd SC7280_CX>, <&gcc GCC_USB30_PRIM_GDSC>; Order matters and thus the order here can't be flipped. > + required-opps = <&rpmhpd_opp_svs>, <>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index d74a4c8..9e3b6ad 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2538,7 +2538,8 @@ interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; - power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + power-domains = <&rpmhpd SC7280_CX>, <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_svs>, <>; resets = <&gcc GCC_USB30_PRIM_BCR>;
Add multi pd support to set performance state for cx domain to maintain minimum corner voltage for USB clocks. Signed-off-by: Sandeep Maheswaram <quic_c_sanm@quicinc.com> --- v2: Changed rpmhd_opp_svs to rmphd_opp_nom for cx domain. arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)