diff mbox series

[03/10] dts: aspeed: ast2600: Support SDR50 for SD device

Message ID 20210922103116.30652-4-chin-ting_kuo@aspeedtech.com (mailing list archive)
State New, archived
Headers show
Series ASPEED SD/eMMC controller clock configuration | expand

Commit Message

Chin-Ting Kuo Sept. 22, 2021, 10:31 a.m. UTC
The maximum frequency for SD controller on AST2600 EVB is
100MHz. In order to achieve 100MHz, sd-uhs-sdr50 property
should be added and the driver will set the SDR50 supported
bit in capability 2 register during probing stage.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
---
 arch/arm/boot/dts/aspeed-ast2600-evb.dts | 2 ++
 1 file changed, 2 insertions(+)

Comments

Andrew Jeffery Oct. 26, 2021, 12:42 a.m. UTC | #1
On Wed, 22 Sep 2021, at 20:01, Chin-Ting Kuo wrote:
> The maximum frequency for SD controller on AST2600 EVB is
> 100MHz. In order to achieve 100MHz, sd-uhs-sdr50 property
> should be added and the driver will set the SDR50 supported
> bit in capability 2 register during probing stage.
>
> Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>

As this is a limitation of the SoC it should be done in aspeed-g6.dtsi. 
Unless I've misunderstood?

Andrew

> ---
>  arch/arm/boot/dts/aspeed-ast2600-evb.dts | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts 
> b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
> index b7eb552640cb..4551dba499c2 100644
> --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
> +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
> @@ -280,6 +280,7 @@
>  &sdhci0 {
>  	status = "okay";
>  	bus-width = <4>;
> +	sd-uhs-sdr50;
>  	max-frequency = <100000000>;
>  	sdhci-drive-type = /bits/ 8 <3>;
>  	sdhci-caps-mask = <0x7 0x0>;
> @@ -292,6 +293,7 @@
>  &sdhci1 {
>  	status = "okay";
>  	bus-width = <4>;
> +	sd-uhs-sdr50;
>  	max-frequency = <100000000>;
>  	sdhci-drive-type = /bits/ 8 <3>;
>  	sdhci-caps-mask = <0x7 0x0>;
> -- 
> 2.17.1
Chin-Ting Kuo Nov. 6, 2021, 10:01 a.m. UTC | #2
> -----Original Message-----
> From: Andrew Jeffery <andrew@aj.id.au>
> Sent: Tuesday, October 26, 2021 8:43 AM
> Subject: Re: [PATCH 03/10] dts: aspeed: ast2600: Support SDR50 for SD device
> 
> 
> 
> On Wed, 22 Sep 2021, at 20:01, Chin-Ting Kuo wrote:
> > The maximum frequency for SD controller on AST2600 EVB is 100MHz. In
> > order to achieve 100MHz, sd-uhs-sdr50 property should be added and the
> > driver will set the SDR50 supported bit in capability 2 register
> > during probing stage.
> >
> > Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> 
> As this is a limitation of the SoC it should be done in aspeed-g6.dtsi.
> Unless I've misunderstood?
> 

Okay, it will be updated in the next patch version.

> Andrew
> 
> > ---
> >  arch/arm/boot/dts/aspeed-ast2600-evb.dts | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
> > b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
> > index b7eb552640cb..4551dba499c2 100644
> > --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
> > +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
> > @@ -280,6 +280,7 @@
> >  &sdhci0 {
> >  	status = "okay";
> >  	bus-width = <4>;
> > +	sd-uhs-sdr50;
> >  	max-frequency = <100000000>;
> >  	sdhci-drive-type = /bits/ 8 <3>;
> >  	sdhci-caps-mask = <0x7 0x0>;
> > @@ -292,6 +293,7 @@
> >  &sdhci1 {
> >  	status = "okay";
> >  	bus-width = <4>;
> > +	sd-uhs-sdr50;
> >  	max-frequency = <100000000>;
> >  	sdhci-drive-type = /bits/ 8 <3>;
> >  	sdhci-caps-mask = <0x7 0x0>;
> > --
> > 2.17.1

Chin-Ting
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index b7eb552640cb..4551dba499c2 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -280,6 +280,7 @@ 
 &sdhci0 {
 	status = "okay";
 	bus-width = <4>;
+	sd-uhs-sdr50;
 	max-frequency = <100000000>;
 	sdhci-drive-type = /bits/ 8 <3>;
 	sdhci-caps-mask = <0x7 0x0>;
@@ -292,6 +293,7 @@ 
 &sdhci1 {
 	status = "okay";
 	bus-width = <4>;
+	sd-uhs-sdr50;
 	max-frequency = <100000000>;
 	sdhci-drive-type = /bits/ 8 <3>;
 	sdhci-caps-mask = <0x7 0x0>;