| Message ID | 20211026064227.2014502-3-anup.patel@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | QEMU RISC-V AIA support | expand |
On Tue, Oct 26, 2021 at 2:43 PM Anup Patel <anup.patel@wdc.com> wrote: > > A hypervsior can optionally take guest external interrupts using typo: hypervisor > SGEIP bit of hip and hie CSRs. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 3 ++- > target/riscv/cpu_bits.h | 3 +++ > target/riscv/csr.c | 18 +++++++++++------- > 3 files changed, 16 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 788fa0b11c..0460a3972b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -365,6 +365,7 @@ static void riscv_cpu_reset(DeviceState *dev) > env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); > } > env->mcause = 0; > + env->miclaim = MIP_SGEIP; > env->pc = env->resetvec; > env->two_stage_lookup = false; > #endif > @@ -598,7 +599,7 @@ static void riscv_cpu_init(Object *obj) > cpu_set_cpustate_pointers(cpu); > > #ifndef CONFIG_USER_ONLY > - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); > + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX); > #endif /* CONFIG_USER_ONLY */ > } > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index cffcd3a5df..8a5a4cde95 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -498,6 +498,8 @@ typedef enum RISCVException { > #define IRQ_S_EXT 9 > #define IRQ_VS_EXT 10 > #define IRQ_M_EXT 11 > +#define IRQ_S_GEXT 12 > +#define IRQ_LOCAL_MAX 13 The IRQ_LOCAL_MAX should be XLEN long, not 13. > > /* mip masks */ > #define MIP_USIP (1 << IRQ_U_SOFT) > @@ -512,6 +514,7 @@ typedef enum RISCVException { > #define MIP_SEIP (1 << IRQ_S_EXT) > #define MIP_VSEIP (1 << IRQ_VS_EXT) > #define MIP_MEIP (1 << IRQ_M_EXT) > +#define MIP_SGEIP (1 << IRQ_S_GEXT) > > /* sip masks */ > #define SIP_SSIP MIP_SSIP > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 9dfc9b5eba..9a0a0c0679 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -408,12 +408,13 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno, > #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) > #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) > #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) > +#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS) > > static const target_ulong delegable_ints = S_MODE_INTERRUPTS | > VS_MODE_INTERRUPTS; > static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; > static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | > - VS_MODE_INTERRUPTS; > + HS_MODE_INTERRUPTS; > #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ > (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ > (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ > @@ -673,7 +674,7 @@ static RISCVException write_mideleg(CPURISCVState *env, int csrno, > { > env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); > if (riscv_has_ext(env, RVH)) { > - env->mideleg |= VS_MODE_INTERRUPTS; > + env->mideleg |= HS_MODE_INTERRUPTS; > } > return RISCV_EXCP_NONE; > } > @@ -689,6 +690,9 @@ static RISCVException write_mie(CPURISCVState *env, int csrno, > target_ulong val) > { > env->mie = (env->mie & ~all_ints) | (val & all_ints); > + if (!riscv_has_ext(env, RVH)) { > + env->mie &= ~MIP_SGEIP; > + } > return RISCV_EXCP_NONE; > } > > @@ -984,7 +988,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno, > } > > if (ret_value) { > - *ret_value &= env->mideleg; > + *ret_value &= env->mideleg & S_MODE_INTERRUPTS; > } > return ret; > } > @@ -1102,7 +1106,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno, > write_mask & hvip_writable_mask); > > if (ret_value) { > - *ret_value &= hvip_writable_mask; > + *ret_value &= VS_MODE_INTERRUPTS; > } > return ret; > } > @@ -1115,7 +1119,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno, > write_mask & hip_writable_mask); > > if (ret_value) { > - *ret_value &= hip_writable_mask; > + *ret_value &= HS_MODE_INTERRUPTS; > } > return ret; > } > @@ -1123,14 +1127,14 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno, > static RISCVException read_hie(CPURISCVState *env, int csrno, > target_ulong *val) > { > - *val = env->mie & VS_MODE_INTERRUPTS; > + *val = env->mie & HS_MODE_INTERRUPTS; > return RISCV_EXCP_NONE; > } > > static RISCVException write_hie(CPURISCVState *env, int csrno, > target_ulong val) > { > - target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); > + target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS); > return write_mie(env, CSR_MIE, newval); > } > Regards, Bin
On Tue, Nov 2, 2021 at 12:22 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel <anup.patel@wdc.com> wrote: > > > > A hypervsior can optionally take guest external interrupts using > > typo: hypervisor Okay, I will update. > > > SGEIP bit of hip and hie CSRs. > > > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > --- > > target/riscv/cpu.c | 3 ++- > > target/riscv/cpu_bits.h | 3 +++ > > target/riscv/csr.c | 18 +++++++++++------- > > 3 files changed, 16 insertions(+), 8 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 788fa0b11c..0460a3972b 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -365,6 +365,7 @@ static void riscv_cpu_reset(DeviceState *dev) > > env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); > > } > > env->mcause = 0; > > + env->miclaim = MIP_SGEIP; > > env->pc = env->resetvec; > > env->two_stage_lookup = false; > > #endif > > @@ -598,7 +599,7 @@ static void riscv_cpu_init(Object *obj) > > cpu_set_cpustate_pointers(cpu); > > > > #ifndef CONFIG_USER_ONLY > > - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); > > + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX); > > #endif /* CONFIG_USER_ONLY */ > > } > > > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > > index cffcd3a5df..8a5a4cde95 100644 > > --- a/target/riscv/cpu_bits.h > > +++ b/target/riscv/cpu_bits.h > > @@ -498,6 +498,8 @@ typedef enum RISCVException { > > #define IRQ_S_EXT 9 > > #define IRQ_VS_EXT 10 > > #define IRQ_M_EXT 11 > > +#define IRQ_S_GEXT 12 > > +#define IRQ_LOCAL_MAX 13 > > The IRQ_LOCAL_MAX should be XLEN long, not 13. The IRQ_LOCAL_MAX here represents local interrupts standardized by the RISC-V privilege spec. This value will change only when more local interrupts are standardized by the RISC-V privilege spec. > > > > > /* mip masks */ > > #define MIP_USIP (1 << IRQ_U_SOFT) > > @@ -512,6 +514,7 @@ typedef enum RISCVException { > > #define MIP_SEIP (1 << IRQ_S_EXT) > > #define MIP_VSEIP (1 << IRQ_VS_EXT) > > #define MIP_MEIP (1 << IRQ_M_EXT) > > +#define MIP_SGEIP (1 << IRQ_S_GEXT) > > > > /* sip masks */ > > #define SIP_SSIP MIP_SSIP > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 9dfc9b5eba..9a0a0c0679 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -408,12 +408,13 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno, > > #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) > > #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) > > #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) > > +#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS) > > > > static const target_ulong delegable_ints = S_MODE_INTERRUPTS | > > VS_MODE_INTERRUPTS; > > static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; > > static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | > > - VS_MODE_INTERRUPTS; > > + HS_MODE_INTERRUPTS; > > #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ > > (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ > > (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ > > @@ -673,7 +674,7 @@ static RISCVException write_mideleg(CPURISCVState *env, int csrno, > > { > > env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); > > if (riscv_has_ext(env, RVH)) { > > - env->mideleg |= VS_MODE_INTERRUPTS; > > + env->mideleg |= HS_MODE_INTERRUPTS; > > } > > return RISCV_EXCP_NONE; > > } > > @@ -689,6 +690,9 @@ static RISCVException write_mie(CPURISCVState *env, int csrno, > > target_ulong val) > > { > > env->mie = (env->mie & ~all_ints) | (val & all_ints); > > + if (!riscv_has_ext(env, RVH)) { > > + env->mie &= ~MIP_SGEIP; > > + } > > return RISCV_EXCP_NONE; > > } > > > > @@ -984,7 +988,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno, > > } > > > > if (ret_value) { > > - *ret_value &= env->mideleg; > > + *ret_value &= env->mideleg & S_MODE_INTERRUPTS; > > } > > return ret; > > } > > @@ -1102,7 +1106,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno, > > write_mask & hvip_writable_mask); > > > > if (ret_value) { > > - *ret_value &= hvip_writable_mask; > > + *ret_value &= VS_MODE_INTERRUPTS; > > } > > return ret; > > } > > @@ -1115,7 +1119,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno, > > write_mask & hip_writable_mask); > > > > if (ret_value) { > > - *ret_value &= hip_writable_mask; > > + *ret_value &= HS_MODE_INTERRUPTS; > > } > > return ret; > > } > > @@ -1123,14 +1127,14 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno, > > static RISCVException read_hie(CPURISCVState *env, int csrno, > > target_ulong *val) > > { > > - *val = env->mie & VS_MODE_INTERRUPTS; > > + *val = env->mie & HS_MODE_INTERRUPTS; > > return RISCV_EXCP_NONE; > > } > > > > static RISCVException write_hie(CPURISCVState *env, int csrno, > > target_ulong val) > > { > > - target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); > > + target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS); > > return write_mie(env, CSR_MIE, newval); > > } > > > > Regards, > Bin Regards, Anup
On Tue, Nov 2, 2021 at 6:24 PM Anup Patel <anup@brainfault.org> wrote: > > On Tue, Nov 2, 2021 at 12:22 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel <anup.patel@wdc.com> wrote: > > > > > > A hypervsior can optionally take guest external interrupts using > > > > typo: hypervisor > > Okay, I will update. > > > > > > SGEIP bit of hip and hie CSRs. > > > > > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > > --- > > > target/riscv/cpu.c | 3 ++- > > > target/riscv/cpu_bits.h | 3 +++ > > > target/riscv/csr.c | 18 +++++++++++------- > > > 3 files changed, 16 insertions(+), 8 deletions(-) > > > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > > index 788fa0b11c..0460a3972b 100644 > > > --- a/target/riscv/cpu.c > > > +++ b/target/riscv/cpu.c > > > @@ -365,6 +365,7 @@ static void riscv_cpu_reset(DeviceState *dev) > > > env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); > > > } > > > env->mcause = 0; > > > + env->miclaim = MIP_SGEIP; > > > env->pc = env->resetvec; > > > env->two_stage_lookup = false; > > > #endif > > > @@ -598,7 +599,7 @@ static void riscv_cpu_init(Object *obj) > > > cpu_set_cpustate_pointers(cpu); > > > > > > #ifndef CONFIG_USER_ONLY > > > - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); > > > + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX); > > > #endif /* CONFIG_USER_ONLY */ > > > } > > > > > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > > > index cffcd3a5df..8a5a4cde95 100644 > > > --- a/target/riscv/cpu_bits.h > > > +++ b/target/riscv/cpu_bits.h > > > @@ -498,6 +498,8 @@ typedef enum RISCVException { > > > #define IRQ_S_EXT 9 > > > #define IRQ_VS_EXT 10 > > > #define IRQ_M_EXT 11 > > > +#define IRQ_S_GEXT 12 > > > +#define IRQ_LOCAL_MAX 13 > > > > The IRQ_LOCAL_MAX should be XLEN long, not 13. > > The IRQ_LOCAL_MAX here represents local interrupts > standardized by the RISC-V privilege spec. This value The standardardized IRQ number is 16. > will change only when more local interrupts are > standardized by the RISC-V privilege spec. We should leave room for platform / custom IRQ as it is already defined by the priv spec. Regards, Bin
On Tue, Nov 2, 2021 at 4:22 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > On Tue, Nov 2, 2021 at 6:24 PM Anup Patel <anup@brainfault.org> wrote: > > > > On Tue, Nov 2, 2021 at 12:22 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel <anup.patel@wdc.com> wrote: > > > > > > > > A hypervsior can optionally take guest external interrupts using > > > > > > typo: hypervisor > > > > Okay, I will update. > > > > > > > > > SGEIP bit of hip and hie CSRs. > > > > > > > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > > > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > > > --- > > > > target/riscv/cpu.c | 3 ++- > > > > target/riscv/cpu_bits.h | 3 +++ > > > > target/riscv/csr.c | 18 +++++++++++------- > > > > 3 files changed, 16 insertions(+), 8 deletions(-) > > > > > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > > > index 788fa0b11c..0460a3972b 100644 > > > > --- a/target/riscv/cpu.c > > > > +++ b/target/riscv/cpu.c > > > > @@ -365,6 +365,7 @@ static void riscv_cpu_reset(DeviceState *dev) > > > > env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); > > > > } > > > > env->mcause = 0; > > > > + env->miclaim = MIP_SGEIP; > > > > env->pc = env->resetvec; > > > > env->two_stage_lookup = false; > > > > #endif > > > > @@ -598,7 +599,7 @@ static void riscv_cpu_init(Object *obj) > > > > cpu_set_cpustate_pointers(cpu); > > > > > > > > #ifndef CONFIG_USER_ONLY > > > > - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); > > > > + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX); > > > > #endif /* CONFIG_USER_ONLY */ > > > > } > > > > > > > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > > > > index cffcd3a5df..8a5a4cde95 100644 > > > > --- a/target/riscv/cpu_bits.h > > > > +++ b/target/riscv/cpu_bits.h > > > > @@ -498,6 +498,8 @@ typedef enum RISCVException { > > > > #define IRQ_S_EXT 9 > > > > #define IRQ_VS_EXT 10 > > > > #define IRQ_M_EXT 11 > > > > +#define IRQ_S_GEXT 12 > > > > +#define IRQ_LOCAL_MAX 13 > > > > > > The IRQ_LOCAL_MAX should be XLEN long, not 13. > > > > The IRQ_LOCAL_MAX here represents local interrupts > > standardized by the RISC-V privilege spec. This value > > The standardardized IRQ number is 16. Max local IRQ as 13 is more conservative and better (IMO) because we are not including any undefined local IRQ. I also totally fine changing max local IRQ to 16 as well. > > > will change only when more local interrupts are > > standardized by the RISC-V privilege spec. > > We should leave room for platform / custom IRQ as it is already > defined by the priv spec. custom local IRQs are not going to be accepted in the first 16 local IRQs. The AIA spec defines a sparse numbering scheme for both standard/custom local IRQs beyond 16. The AIA spec will also maintain a table of defined local IRQs. IMO, we should deal with custom local IRQs as when they show up and standard local IRQs should always get first class treatment. Regards, Anup > > Regards, > Bin
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 788fa0b11c..0460a3972b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -365,6 +365,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); } env->mcause = 0; + env->miclaim = MIP_SGEIP; env->pc = env->resetvec; env->two_stage_lookup = false; #endif @@ -598,7 +599,7 @@ static void riscv_cpu_init(Object *obj) cpu_set_cpustate_pointers(cpu); #ifndef CONFIG_USER_ONLY - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX); #endif /* CONFIG_USER_ONLY */ } diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index cffcd3a5df..8a5a4cde95 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -498,6 +498,8 @@ typedef enum RISCVException { #define IRQ_S_EXT 9 #define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_LOCAL_MAX 13 /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) @@ -512,6 +514,7 @@ typedef enum RISCVException { #define MIP_SEIP (1 << IRQ_S_EXT) #define MIP_VSEIP (1 << IRQ_VS_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) +#define MIP_SGEIP (1 << IRQ_S_GEXT) /* sip masks */ #define SIP_SSIP MIP_SSIP diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9dfc9b5eba..9a0a0c0679 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -408,12 +408,13 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno, #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) +#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS) static const target_ulong delegable_ints = S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS; static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | - VS_MODE_INTERRUPTS; + HS_MODE_INTERRUPTS; #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ @@ -673,7 +674,7 @@ static RISCVException write_mideleg(CPURISCVState *env, int csrno, { env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); if (riscv_has_ext(env, RVH)) { - env->mideleg |= VS_MODE_INTERRUPTS; + env->mideleg |= HS_MODE_INTERRUPTS; } return RISCV_EXCP_NONE; } @@ -689,6 +690,9 @@ static RISCVException write_mie(CPURISCVState *env, int csrno, target_ulong val) { env->mie = (env->mie & ~all_ints) | (val & all_ints); + if (!riscv_has_ext(env, RVH)) { + env->mie &= ~MIP_SGEIP; + } return RISCV_EXCP_NONE; } @@ -984,7 +988,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno, } if (ret_value) { - *ret_value &= env->mideleg; + *ret_value &= env->mideleg & S_MODE_INTERRUPTS; } return ret; } @@ -1102,7 +1106,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno, write_mask & hvip_writable_mask); if (ret_value) { - *ret_value &= hvip_writable_mask; + *ret_value &= VS_MODE_INTERRUPTS; } return ret; } @@ -1115,7 +1119,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno, write_mask & hip_writable_mask); if (ret_value) { - *ret_value &= hip_writable_mask; + *ret_value &= HS_MODE_INTERRUPTS; } return ret; } @@ -1123,14 +1127,14 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno, static RISCVException read_hie(CPURISCVState *env, int csrno, target_ulong *val) { - *val = env->mie & VS_MODE_INTERRUPTS; + *val = env->mie & HS_MODE_INTERRUPTS; return RISCV_EXCP_NONE; } static RISCVException write_hie(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); + target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS); return write_mie(env, CSR_MIE, newval); }