Message ID | 1635820355-27009-4-git-send-email-hongxing.zhu@nxp.com |
---|---|
State | Superseded |
Headers | show |
Series | Add the imx8m pcie phy driver and imx8mm pcie support | expand |
On Tue, 02 Nov 2021 10:32:30 +0800, Richard Zhu wrote: > i.MX8MM PCIe has the PHY. Add a PHY phandle and name properties > in the binding document. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> > Reviewed-by: Tim Harvey <tharvey@gateworks.com> > Tested-by: Tim Harvey <tharvey@gateworks.com> > --- > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 2911e565b260..46b5446f5791 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -128,6 +128,12 @@ properties: enum: [1, 2, 3, 4] default: 1 + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + reset-gpio: description: Should specify the GPIO for controlling the PCI bus device reset signal. It's not polarity aware and defaults to active-low reset